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1. 发明授权

US09202005B2 Development and debug environment in a constrained random verification 有权
标题翻译：开发和调试环境在受限的随机验证中
公开(公告)号：US09202005B2
公开(公告)日：2015-12-01
申请号：US14472058
申请日：2014-08-28
申请人： Synopsys, Inc.
发明人： Dhiraj Goswami , Aijun Hu , Na Xing , Jason Chung-Shih Chen , Ngai Ngai William Hung
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009
摘要： A design verification workstation contains both debug and constraint solver capabilities during simulation of a design under test. The design verification workstation is configured to allow the user to debug constraints, stop the constraint solver, navigate problems and variables, and make modifications on-the fly during the simulation to constraint information. Additionally, in some embodiments, the design verification workstation may allow a user to use a constraint solver to experiment if the modifications will lead to desired test stimulus. Since this debug process happens during simulation, users do not need to recompile the test case. Additionally, once a user is satisfied with the modifications made to the simulation, the modification could be saved for future usage.
摘要翻译：设计验证工作站在模拟被测设计期间包含调试和约束求解器功能。设计验证工作站被配置为允许用户调试约束，停止约束求解器，导航问题和变量，并在仿真期间对约束信息进行修改。另外，在一些实施例中，设计验证工作站可以允许用户使用约束求解器来实验，如果修改将导致期望的测试刺激。由于调试过程在模拟过程中发生，用户无需重新编译测试用例。另外，一旦用户对对模拟进行的修改满意，则可以节省修改以供将来使用。

2. 发明授权

US09958917B1 Generalized resettable memory 有权
公开(公告)号：US09958917B1
公开(公告)日：2018-05-01
申请号：US15368457
申请日：2016-12-02
申请人： Synopsys, Inc.
发明人： Ngai Ngai William Hung , Dhiraj Goswami
IPC分类号： G11C7/10 , G06F1/24 , G11C7/22 , G06F13/10 , G06F13/12 , G06F11/30
CPC分类号： G06F1/24 , G06F11/3037 , G06F11/3055 , G06F13/105 , G06F13/124 , G11C7/20 , G11C29/16 , G11C29/46 , G11C29/50012
摘要： Disclosed is a resettable memory device including a memory unit, a reset status indicator circuit, a logic sampling circuit, and a multiplexer for performing a reset function. The memory unit includes cells for storing states of signals in a design under test. The reset status indicator stores states of indicators indicating whether corresponding cells should be reset or not. Responsive to the reset status indicator indicating that the value of the cell should not be reset, the multiplexer receives the value stored in the cell and outputs the retrieved value from the cell. Responsive to the reset status indicator indicating that the value of the cell should be reset, the multiplexer outputs a reset value instead of the value stored in the cell. The reset value may be changed by the logic sampling circuit at different time periods or certain logic conditions, and output through the multiplexer.

3. 发明申请

US20140282343A1 PRIORITIZED SOFT CONSTRAINT SOLVING 有权
标题翻译：优化软约束解
公开(公告)号：US20140282343A1
公开(公告)日：2014-09-18
申请号：US14209579
申请日：2014-03-13
申请人： Synopsys, Inc.
发明人： Ganapathy Parthasarathy , Dhiraj Goswami
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： A design problem can include a mixture of hard constraints and soft constraints. The soft constraints can be prioritized and the design problem solved. One or more soft constraints may not be honored in the midst of the solving of the design problem. Debugging can be performed and the unsatisfied soft constraints identified. Root-cause analysis can evaluate the challenges within the design problem which caused soft constraints not to be honored.
摘要翻译：设计问题可能包括硬约束和软约束的混合。可以优先考虑软限制，解决设计问题。在解决设计问题的过程中，一个或多个软约束可能无法兑现。可以执行调试，并确定不满意的软约束。根本原因分析可以评估设计问题中的挑战，导致软约束不被尊重。

4. 发明申请

US20140282316A1 SOLVING MULTIPLICATION CONSTRAINTS BY FACTORIZATION 有权
标题翻译：通过制造解决多项约束
公开(公告)号：US20140282316A1
公开(公告)日：2014-09-18
申请号：US13802450
申请日：2013-03-13
申请人： SYNOPSYS, INC.
发明人： Vijay Anand Korthikanti , Dhiraj Goswami
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/504
摘要： A design description for verification includes a set of constraints on random variables within the design description. The set of constraints includes at least one multiplication constraint involving at least two random variables. A computer-based tool obtains designs and analyzes the design description to find the set of constraints and identify the multiplication constraint. The computer-based tool then performs factorization to solve for the multiplication constraint and to determine a set of potentially valid factoring values for the random variables used in the multiplication constraint. The design problem is then solved by the computer-based tool using the factoring values. If two multiplication constraints involve a common variable, the factorization finds a set of common factoring values between the two multiplication constraints to use for the common variable.
摘要翻译：用于验证的设计描述包括对设计描述内的随机变量的一组约束。所述约束集包括至少一个涉及至少两个随机变量的乘法约束。基于计算机的工具获得设计并分析设计描述以找到约束集并且识别乘法约束。然后，基于计算机的工具执行分解以解决乘法约束并且确定用于乘法约束中使用的随机变量的一组潜在有效的因式分解值。然后通过基于计算机的工具使用因式分解值来解决设计问题。如果两个乘法约束涉及一个公共变量，则因式分解可以找到用于公共变量的两个乘法约束之间的一组公共因子分解值。

5. 发明申请

US20160034624A1 OPTIMIZING CONSTRAINT SOLVING BY REWRITING AT LEAST ONE BIT-SLICE CONSTRAINT 审中-公开
标题翻译：最优解约束可以通过修改一个单一的矩阵约束来解决
公开(公告)号：US20160034624A1
公开(公告)日：2016-02-04
申请号：US14881029
申请日：2015-10-12
申请人： Synopsys, Inc.
发明人： Ngai Ngai William Hung , Qiang Qiang , Guillermo R. Maturana , Jasvinder Singh , Dhiraj Goswami
IPC分类号： G06F17/50 , G06F7/58
CPC分类号： G06F17/5045 , G06F7/582 , G06F17/11 , G06F2217/06
摘要： Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. A constraint solver can receive a set of constraints that is expected to cause performance problems when the system assigns random values to the set of random variables in a manner that satisfies the set of constraints. For example, modulo constraints and bit-slice constraints can cause the system to perform excessive backtracking when the system attempts to assign random values to the set of random variables in a manner that satisfies the set of constraints. The system can rewrite the set of constraints to obtain a new set of constraints that is expected to reduce and/or avoid the performance problems. The system can then assign random values to the set of random variables based on the new set of constraints.
摘要翻译：描述用于将随机值分配给一组随机变量的方法和装置，使得分配的随机值满足一组约束。约束求解器可以接收一组约束，当系统以满足约束集合的方式将随机值分配给随机变量集合时，预期会导致性能问题。例如，当系统尝试以满足约束集合的方式将随机值分配给随机变量集时，模约束和位片约束可导致系统执行过多的回溯。系统可以重写一组约束以获得预期会减少和/或避免性能问题的新的一组约束。然后，系统可以基于新的约束集将随机值分配给随机变量集合。

6. 发明授权

US09098665B2 Prioritized soft constraint solving 有权
标题翻译：优先软约束求解
公开(公告)号：US09098665B2
公开(公告)日：2015-08-04
申请号：US14209579
申请日：2014-03-13
申请人： Synopsys, Inc.
发明人： Ganapathy Parthasarathy , Dhiraj Goswami
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： A design problem can include a mixture of hard constraints and soft constraints. The soft constraints can be prioritized and the design problem solved. One or more soft constraints may not be honored in the midst of the solving of the design problem. Debugging can be performed and the unsatisfied soft constraints identified. Root-cause analysis can evaluate the challenges within the design problem which caused soft constraints not to be honored.
摘要翻译：设计问题可能包括硬约束和软约束的混合。可以优先考虑软限制，解决设计问题。在解决设计问题的过程中，一个或多个软约束可能无法兑现。可以执行调试，并确定不满意的软约束。根本原因分析可以评估设计问题中的挑战，导致软约束不被尊重。

7. 发明授权

US08904320B2 Solving multiplication constraints by factorization 有权
标题翻译：通过因式分解求解乘数约束
公开(公告)号：US08904320B2
公开(公告)日：2014-12-02
申请号：US13802450
申请日：2013-03-13
申请人： Synopsys, Inc.
发明人： Vijay Anand Korthikanti , Dhiraj Goswami
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/504
摘要： A design description for verification includes a set of constraints on random variables within the design description. The set of constraints includes at least one multiplication constraint involving at least two random variables. A computer-based tool obtains designs and analyzes the design description to find the set of constraints and identify the multiplication constraint. The computer-based tool then performs factorization to solve for the multiplication constraint and to determine a set of potentially valid factoring values for the random variables used in the multiplication constraint. The design problem is then solved by the computer-based tool using the factoring values. If two multiplication constraints involve a common variable, the factorization finds a set of common factoring values between the two multiplication constraints to use for the common variable.
摘要翻译：用于验证的设计描述包括对设计描述内的随机变量的一组约束。所述约束集包括至少一个涉及至少两个随机变量的乘法约束。基于计算机的工具获得设计并分析设计描述以找到约束集并且识别乘法约束。然后，基于计算机的工具执行分解以解决乘法约束并且确定用于乘法约束中使用的随机变量的一组潜在有效的因式分解值。然后通过基于计算机的工具使用因式分解值来解决设计问题。如果两个乘法约束涉及一个公共变量，则因式分解可以找到用于公共变量的两个乘法约束之间的一组公共因子分解值。

8. 发明授权

US10325046B2 Formal method for clock tree analysis and optimization 有权
公开(公告)号：US10325046B2
公开(公告)日：2019-06-18
申请号：US15705784
申请日：2017-09-15
申请人： Synopsys, Inc.
发明人： Lingyi Liu , Ngai Ngai William Hung , Sitanshu Seth , Leonid Alexander Broukhis , Dhiraj Goswami
IPC分类号： G06F9/455 , G06F17/50
摘要： Configuring a hardware verification system includes receiving first data representing a first integrated circuit design configured to operate via a first clock signal derived from a second clock signal and a third signal generated by the second clock signal. The computer transforms the first data into second data representing a second design that includes functionality of the first design. The transformation replaces the first clock signal with the second clock signal. A first Boolean function is defined by first and second values of the third signal corresponding to a first transition of the second clock signal being in a same direction as a transition of the first clock signal. A second Boolean function is defined by the first and second values of the third signal corresponding to a second transition of the second clock signal being in a direction opposite to the associated transition of the first clock signal.

9. 发明申请

US20180082004A1 FORMAL METHOD FOR CLOCK TREE ANALYSIS AND OPTIMIZATION 审中-公开
公开(公告)号：US20180082004A1
公开(公告)日：2018-03-22
申请号：US15705784
申请日：2017-09-15
申请人： Synopsys, Inc.
发明人： Lingyi Liu , Ngai Ngai William Hung , Sitanshu Seth , Leonid Alexander Broukhis , Dhiraj Goswami
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5027 , G06F17/504 , G06F17/5054 , G06F2217/62
摘要： Configuring a hardware verification system includes receiving first data representing a first integrated circuit design configured to operate via a first clock signal derived from a second clock signal and a third signal generated by the second clock signal. The computer transforms the first data into second data representing a second design that includes functionality of the first design. The transformation replaces the first clock signal with the second clock signal. A first Boolean function is defined by first and second values of the third signal corresponding to a first transition of the second clock signal being in a same direction as a transition of the first clock signal. A second Boolean function is defined by the first and second values of the third signal corresponding to a second transition of the second clock signal being in a direction opposite to the associated transition of the first clock signal.

10. 发明申请

US20140068533A1 INFORMATION THEORETIC SUBGRAPH CACHING 审中-公开
标题翻译：信息理论基本过程
公开(公告)号：US20140068533A1
公开(公告)日：2014-03-06
申请号：US13766749
申请日：2013-02-13
申请人： SYNOPSYS, INC.
发明人： Dhiraj Goswami , Ngai Ngai William Hung
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022 , G06F17/504
摘要： Computer-implemented techniques are disclosed for verifying circuit designs using subgraph caching. A device under test (DUT) is modeled as a graph. The graph is partitioned into one or more subgraphs and problems are generated for each subgraph. Graph and subgraph problem generation is repeated numerous times throughout the verification process. Problems and sub-problems are generated and solved. When a subgraph problem is solved, the problem's variables, values, and information can be stored in a cache. The storage can be based on entropy of variables used in the graph and subgraph problems. The subgraph problem storage cache can be searched for previously stored problems which match another problem in need of a solution. By retrieving subproblem variables, values, and information from the cache, the computational overhead of circuit design verification is reduced as problems are reused. Caching can be accomplished using an information theoretic approach.
摘要翻译：公开了使用子图缓存来验证电路设计的计算机实现的技术。被测设备（DUT）被建模为图形。图形被划分成一个或多个子图，并为每个子图生成问题。图形和子图问题的产生在整个验证过程中重复了很多次。产生和解决问题和子问题。当解决子图问题时，问题的变量，值和信息可以存储在缓存中。存储可以基于图中使用的变量的熵和子图问题。子图问题存储缓存可以搜索与需要解决方案的另一个问题相匹配的先前存储的问题。通过从缓存中检索子问题变量，值和信息，减少了电路设计验证的计算开销，因为问题被重用。可以使用信息理论方法来实现缓存。

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