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1. 发明授权

US08577948B2 Split path multiply accumulate unit 有权
标题翻译：分路径乘积累积单位
公开(公告)号：US08577948B2
公开(公告)日：2013-11-05
申请号：US12886012
申请日：2010-09-20
申请人： Suresh Srinivasan , Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Vasantha K. Erraguntla
发明人： Suresh Srinivasan , Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Vasantha K. Erraguntla
IPC分类号： G06F7/483
CPC分类号： G06F9/3893 , G06F7/483 , G06F7/5443 , G06F9/30014 , G06F9/30036
摘要： In one embodiment, a processor includes a multiply-accumulate (MAC) unit having a first path to handle execution of an instruction if a difference between at least a portion of first and second operands and a third operand is less than a threshold value, and a second path to handle the instruction execution if the difference is greater than the threshold value. Based on the difference, at least part of the third operand is to be provided to a multiplier of the MAC unit or to a compressor of the second path. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，如果第一和第二操作数的至少一部分与第三操作数之间的差小于阈值，则处理器包括具有第一路径以处理指令的执行的乘法累加（MAC）单元，以及如果差值大于阈值，则处理指令执行的第二路径。基于该差异，第三操作数的至少一部分将被提供给MAC单元的乘法器或第二路径的压缩器。描述和要求保护其他实施例。

2. 发明申请

US20100082718A1 COMBINED SET BIT COUNT AND DETECTOR LOGIC 有权
标题翻译：组合设置位计数和检测器逻辑
公开(公告)号：US20100082718A1
公开(公告)日：2010-04-01
申请号：US12242727
申请日：2008-09-30
申请人： Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Shay Gueron , Vasantha K. Erraguntla
发明人： Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Shay Gueron , Vasantha K. Erraguntla
IPC分类号： G06F7/00
CPC分类号： G06F7/74 , G06F7/607
摘要： A merged datapath for PopCount and BitScan is described. A hardware circuit includes a compressor tree utilized for a PopCount function, which is reused by a BitScan function (e.g., bit scan forward (BSF) or bit scan reverse (BSR)). Selector logic enables the compressor tree to operate on an input word for the PopCount or BitScan operation, based on a microprocessor instruction. The input word is encoded if a BitScan operation is selected. The compressor tree receives the input word, operates on the bits as though all bits have same level of significance (e.g., for an N-bit input word, the input word is treated as N one-bit inputs). The result of the compressor tree circuit is a binary value representing a number related to the operation performed (the number of set bits for PopCount, or the bit position of the first set bit encountered by scanning the input word).
摘要翻译：描述了PopCount和BitScan的合并数据路径。硬件电路包括用于PopCount功能的压缩器树，其由BitScan功能（例如，位扫描前向（BSF）或位扫描反向（BSR））重用。选择器逻辑使压缩器树能够基于微处理器指令对PopCount或BitScan操作的输入字进行操作。如果选择了BitScan操作，则输入字被编码。压缩器树接收输入字，对位进行操作，好像所有位具有相同的重要程度（例如，对于N位输入字，输入字被视为N个一位输入）。压缩器树电路的结果是表示与执行的操作有关的数字的二进制值（PopCount的设置位数，或通过扫描输入字所遇到的第一组位的位位置）。

3. 发明授权

US08214414B2 Combined set bit count and detector logic 有权
标题翻译：组合位计数和检测器逻辑
公开(公告)号：US08214414B2
公开(公告)日：2012-07-03
申请号：US12242727
申请日：2008-09-30
申请人： Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Shay Gueron , Vasantha K. Erraguntla
发明人： Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Shay Gueron , Vasantha K. Erraguntla
IPC分类号： G06F15/00
CPC分类号： G06F7/74 , G06F7/607
摘要： A merged datapath for PopCount and BitScan is described. A hardware circuit includes a compressor tree utilized for a PopCount function, which is reused by a BitScan function (e.g., bit scan forward (BSF) or bit scan reverse (BSR)). Selector logic enables the compressor tree to operate on an input word for the PopCount or BitScan operation, based on a microprocessor instruction. The input word is encoded if a BitScan operation is selected. The compressor tree receives the input word, operates on the bits as though all bits have same level of significance (e.g., for an N-bit input word, the input word is treated as N one-bit inputs). The result of the compressor tree circuit is a binary value representing a number related to the operation performed (the number of set bits for PopCount, or the bit position of the first set bit encountered by scanning the input word).
摘要翻译：描述了PopCount和BitScan的合并数据路径。硬件电路包括用于PopCount功能的压缩器树，其由BitScan功能（例如，位扫描前向（BSF）或位扫描反向（BSR））重用。选择器逻辑使压缩器树能够基于微处理器指令对PopCount或BitScan操作的输入字进行操作。如果选择了BitScan操作，则输入字被编码。压缩器树接收输入字，对位进行操作，好像所有位具有相同的重要程度（例如，对于N位输入字，输入字被视为N个一位输入）。压缩器树电路的结果是表示与执行的操作有关的数字的二进制值（PopCount的设置位数，或通过扫描输入字所遇到的第一组位的位位置）。

4. 发明授权

US07181544B2 Network protocol engine 有权
标题翻译：网络协议引擎
公开(公告)号：US07181544B2
公开(公告)日：2007-02-20
申请号：US10234492
申请日：2002-09-03
申请人： Sriram R. Vangal , Yatin Hoskote , Nitin Y. Borkar , Jianping Xu , Vasantha K. Erraguntla , Shekhar Y. Borkar
发明人： Sriram R. Vangal , Yatin Hoskote , Nitin Y. Borkar , Jianping Xu , Vasantha K. Erraguntla , Shekhar Y. Borkar
IPC分类号： G06F15/16
CPC分类号： H04L69/22 , H04L69/10 , H04L69/12
摘要： Packet processing techniques that can be used, for example, by a network protocol off-load engine. For example, the techniques may be used in an engine that performs transmission control protocol (TCP) operations for received packets for a host.
摘要翻译：可以使用例如由网络协议卸载引擎使用的分组处理技术。例如，这些技术可以用于为主机的接收分组执行传输控制协议（TCP）操作的引擎中。

5. 发明授权

US07324540B2 Network protocol off-load engines 有权
标题翻译：网络协议卸载引擎
公开(公告)号：US07324540B2
公开(公告)日：2008-01-29
申请号：US10334733
申请日：2002-12-31
申请人： Sriram R. Vangal , Yatin Hoskote , Vasantha K. Erraguntla , Jianping Xu
发明人： Sriram R. Vangal , Yatin Hoskote , Vasantha K. Erraguntla , Jianping Xu
IPC分类号： H04L12/56
CPC分类号： H04L67/1002 , H04L69/12 , H04L69/22
摘要： The disclosure describes techniques for coordinating operation of multiple network protocol off-load engines (e.g., Transport Control Protocol (TCP) off-load engines).
摘要翻译：本公开描述了用于协调多个网络协议卸载引擎（例如，传输控制协议（TCP）卸载引擎）的操作的技术。

6. 发明授权

US07016354B2 Packet-based clock signal 失效
标题翻译：基于分组的时钟信号
公开(公告)号：US07016354B2
公开(公告)日：2006-03-21
申请号：US10234489
申请日：2002-09-03
申请人： Sriram R. Vangal , Yatin Hoskote , Nitin Y. Borkar , Jianping Xu , Vasantha K. Erraguntla , Shekhar Y. Borkar
发明人： Sriram R. Vangal , Yatin Hoskote , Nitin Y. Borkar , Jianping Xu , Vasantha K. Erraguntla , Shekhar Y. Borkar
IPC分类号： H04L12/56
CPC分类号： H04L69/16 , H04J3/0688 , H04L69/161 , H04L69/22
摘要： In general, in one aspect, the disclosure describes a method for use in packet processing. The method can include receiving at least a portion of at least one packet and, based on the at least a portion of the at least one packet, determining a clock signal to provide to processing logic that processes the at least one packet.
摘要翻译：一般来说，一方面，本公开描述了一种在分组处理中使用的方法。该方法可以包括接收至少一个分组的至少一部分，并且基于至少一个分组的至少一部分，确定时钟信号以提供处理至少一个分组的处理逻辑。

7. 发明授权

US07668165B2 Hardware-based multi-threading for packet processing 有权
标题翻译：基于硬件的多线程数据包处理
公开(公告)号：US07668165B2
公开(公告)日：2010-02-23
申请号：US10814496
申请日：2004-03-31
申请人： Yatin Hoskote , Sriram R. Vangal , Vasantha K. Erraguntla , Nitin Y. Borkar
发明人： Yatin Hoskote , Sriram R. Vangal , Vasantha K. Erraguntla , Nitin Y. Borkar
IPC分类号： H04L12/28 , H04L12/56 , G06F9/46 , G06F13/00
CPC分类号： H04L45/745 , H04L49/90 , H04L69/12 , H04L69/32
摘要： Methods and apparatus for processing transmission control protocol (TCP) packets using hardware-based multi-threading techniques. Inbound and outbound TCP packet are processed using a multi-threaded TCP offload engine (TOE). The TOE includes an execution core comprising a processing engine, a scheduler, an on-chip cache, a host memory interface, a host interface, and a network interface controller (NIC) interface. In one embodiment, the TOE is embodied as a memory controller hub (MCH) component of a platform chipset. The TOE may further include an integrated direct memory access (DMA) controller, or the DMA controller may be embodied as separate circuitry on the MCH. In one embodiment, inbound packets are queued in an input buffer, the headers are provided to the scheduler, and the scheduler arbitrates thread execution on the processing engine. Concurrently, DMA payload data transfers are queued and asynchronously performed in a manner that hides memory latencies. In one embodiment, the technique can process typical-size TCP packets at 10 Gbps or greater line speeds.
摘要翻译：使用基于硬件的多线程技术来处理传输控制协议（TCP）分组的方法和装置。使用多线程TCP卸载引擎（TOE）处理入站和出站TCP数据包。 TOE包括执行核心，其包括处理引擎，调度器，片上高速缓存，主机存储器接口，主机接口和网络接口控制器（NIC）接口。在一个实施例中，TOE被实现为平台芯片组的存储器控制器集线器（MCH）组件。 TOE还可以包括集成的直接存储器访问（DMA）控制器，或者DMA控制器可以被实现为MCH上的单独的电路。在一个实施例中，入站分组在输入缓冲器中排队，将报头提供给调度器，并且调度器对处理引擎上的线程执行进行仲裁。同时，DMA有效载荷数据传输以隐藏内存延迟的方式进行排队和异步执行。在一个实施例中，该技术可以处理10Gbps或更高线速度的典型大小的TCP分组。

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