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1. 发明申请

US20130185516A1 Use of Loop and Addressing Mode Instruction Set Semantics to Direct Hardware Prefetching 审中-公开
标题翻译：使用循环和寻址模式指令集语义来直接硬件预取
公开(公告)号：US20130185516A1
公开(公告)日：2013-07-18
申请号：US13350914
申请日：2012-01-16
申请人： Peter G. Sassone , Suman Mamidi , Elizabeth Abraham , Suresh K. Venkumahanti , Lucian Codrescu
发明人： Peter G. Sassone , Suman Mamidi , Elizabeth Abraham , Suresh K. Venkumahanti , Lucian Codrescu
IPC分类号： G06F12/12
CPC分类号： G06F9/30043 , G06F9/30047 , G06F9/3455 , G06F9/381 , G06F9/383 , G06F12/0862 , G06F2212/6026 , Y02D10/13
摘要： Systems and methods for prefetching cache lines into a cache coupled to a processor. A hardware prefetcher is configured to recognize a memory access instruction as an auto-increment-address (AIA) memory access instruction, infer a stride value from an increment field of the AIA instruction, and prefetch lines into the cache based on the stride value. Additionally or alternatively, the hardware prefetcher is configured to recognize that prefetched cache lines are part of a hardware loop, determine a maximum loop count of the hardware loop, and a remaining loop count as a difference between the maximum loop count and a number of loop iterations that have been completed, select a number of cache lines to prefetch, and truncate an actual number of cache lines to prefetch to be less than or equal to the remaining loop count, when the remaining loop count is less than the selected number of cache lines.
摘要翻译：将高速缓存线预取到耦合到处理器的高速缓存中的系统和方法。硬件预取器被配置为将存储器访问指令识别为自动递增地址（AIA）存储器访问指令，从AIA指令的增量字段推断步幅值，并且基于步幅值将预取行预取到高速缓存中。另外或替代地，硬件预取器被配置为识别预取的高速缓存行是硬件循环的一部分，确定硬件循环的最大循环计数，以及剩余循环计数作为最大循环计数和循环数之间的差已经完成的迭代，当剩余循环数小于选定数量的缓存时，选择要预取的高速缓存行数，并将实际数量的缓存行预截取为小于或等于剩余循环计数线条。

2. 发明授权

US08874884B2 Selective writing of branch target buffer when number of instructions in cache line containing branch instruction is less than threshold 有权
标题翻译：当包含分支指令的高速缓存行中的指令数小于阈值时，分支目标缓冲区的选择性写入
公开(公告)号：US08874884B2
公开(公告)日：2014-10-28
申请号：US13289007
申请日：2011-11-04
申请人： Suresh K. Venkumahanti , Lucian Codrescu , Suman Mamidi
发明人： Suresh K. Venkumahanti , Lucian Codrescu , Suman Mamidi
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3844
摘要： A method includes executing a branch instruction and determining if a branch is taken. The method further includes evaluating a number of instructions associated with the branch instruction. Upon determining that the branch is taken, the method includes selectively writing an entry into a branch target buffer that corresponds to the taken branch responsive to determining that the number of instructions is less than a threshold.
摘要翻译：一种方法包括执行分支指令并确定是否采用分支。该方法还包括评估与分支指令相关联的多个指令。在确定分支被采取时，该方法包括响应于确定指令数量小于阈值而选择性地将条目写入对应于所采取的分支的分支目标缓冲器。

3. 发明申请

US20130185515A1 Utilizing Negative Feedback from Unexpected Miss Addresses in a Hardware Prefetcher 审中-公开
标题翻译：在硬件预取器中利用意外错误地址的否定反馈
公开(公告)号：US20130185515A1
公开(公告)日：2013-07-18
申请号：US13350909
申请日：2012-01-16
申请人： Peter G. Sassone , Suman Mamidi , Elizabeth Abraham , Suresh K. Venkumahanti , Lucian Codrescu
发明人： Peter G. Sassone , Suman Mamidi , Elizabeth Abraham , Suresh K. Venkumahanti , Lucian Codrescu
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： Systems and methods for populating a cache using a hardware prefetcher are disclosed. A method for prefetching cache entries includes determining an initial stride value based on at least a first and second demand miss address in the cache, verifying the initial stride value based on a third demand miss address in the cache, prefetching a predetermined number of cache entries based on the verified initial stride value, determining an expected next miss address in the cache based on the verified initial stride value and addresses of the prefetched cache entries; and confirming the verified initial stride value based on comparing the expected next miss address to a next demand miss address in the cache. If the verified initial stride value is confirmed, additional cache entries are prefetched. If the verified initial stride value is not confirmed, further prefetching is stalled and an alternate stride value is determined.
摘要翻译：公开了使用硬件预取器填充高速缓存的系统和方法。用于预取高速缓存条目的方法包括基于高速缓存中的至少第一和第二请求未命中地址来确定初始步幅值，基于高速缓存中的第三请求未命中地址来验证初始步幅值，预取数量的高速缓存条目基于所验证的初始步幅值，基于所述经验证的初始步幅值和所述预取高速缓存条目的地址来确定所述高速缓存中的预期下一未命中地址; 并且基于将预期的下一个未命中地址与高速缓存中的下一个请求未命中地址进行比较来确认已验证的初始步幅值。如果确认了验证的初始步幅值，则预取额外的高速缓存条目。如果验证的初始步幅值未被确认，则进一步预取停止并且确定替代步幅值。

4. 发明申请

US20130117535A1 Selective Writing of Branch Target Buffer 有权
标题翻译：选择性写入分支目标缓冲区
公开(公告)号：US20130117535A1
公开(公告)日：2013-05-09
申请号：US13289007
申请日：2011-11-04
申请人： Suresh K. Venkumahanti , Lucian Codrescu , Suman Mamidi
发明人： Suresh K. Venkumahanti , Lucian Codrescu , Suman Mamidi
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3806 , G06F9/3844
摘要： A method includes executing a branch instruction and determining if a branch is taken. The method further includes evaluating a number of instructions associated with the branch instruction. Upon determining that the branch is taken, the method includes selectively writing an entry into a branch target buffer that corresponds to the taken branch responsive to determining that the number of instructions is less than a threshold.
摘要翻译：一种方法包括执行分支指令并确定是否采用分支。该方法还包括评估与分支指令相关联的多个指令。在确定分支被采取时，该方法包括响应于确定指令数量小于阈值而选择性地将条目写入对应于所采取的分支的分支目标缓冲器。

5. 发明授权

US09824013B2 Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processors 有权
公开(公告)号：US09824013B2
公开(公告)日：2017-11-21
申请号：US13466359
申请日：2012-05-08
申请人： Christopher Edward Koob , Ajay Anant Ingle , Lucian Codrescu , Suresh K. Venkumahanti
发明人： Christopher Edward Koob , Ajay Anant Ingle , Lucian Codrescu , Suresh K. Venkumahanti
IPC分类号： G06F12/08 , G06F12/0842 , G06F12/0846 , G06F12/0864
CPC分类号： G06F12/0842 , G06F12/0848 , G06F12/0864
摘要： Systems and methods for allocation of cache lines in a shared partitioned cache of a multi-threaded processor. A memory management unit is configured to determine attributes associated with an address for a cache entry associated with a processing thread to be allocated in the cache. A configuration register is configured to store cache allocation information based on the determined attributes. A partitioning register is configured to store partitioning information for partitioning the cache into two or more portions. The cache entry is allocated into one of the portions of the cache based on the configuration register and the partitioning register.

6. 发明授权

US08972642B2 Low latency two-level interrupt controller interface to multi-threaded processor 有权
标题翻译：低延迟两级中断控制器接口到多线程处理器
公开(公告)号：US08972642B2
公开(公告)日：2015-03-03
申请号：US13252670
申请日：2011-10-04
申请人： Suresh K. Venkumahanti , Lucian Codrescu , Erich James Plondke , Xufeng Chen , Peixin Zhong
发明人： Suresh K. Venkumahanti , Lucian Codrescu , Erich James Plondke , Xufeng Chen , Peixin Zhong
IPC分类号： G06F13/24 , G06F13/32
CPC分类号： G06F13/24
摘要： Systems and method for reducing interrupt latency time in a multi-threaded processor. A first interrupt controller is coupled to the multi-threaded processor. A second interrupt controller is configured to communicate a first interrupt and a first vector identifier to the first interrupt controller, wherein the first interrupt controller is configured to process the first interrupt and the first vector identifier and send the processed interrupt to a thread in the multi-threaded processor. Logic is configured to determine when the multi-threaded processor is ready to receive a second interrupt. A dedicated line is used to communicate an indication to the second interrupt controller that the multi-threaded processor is ready to receive the second interrupt.
摘要翻译：用于减少多线程处理器中的中断延迟时间的系统和方法。第一个中断控制器耦合到多线程处理器。第二中断控制器被配置为将第一中断和第一向量标识符传送到第一中断控制器，其中第一中断控制器被配置为处理第一中断和第一向量标识符，并将经处理的中断发送到多路复用器中的线程线程处理器逻辑配置为确定多线程处理器何时准备好接收第二个中断。专用线路用于向第二中断控制器通知多线程处理器准备好接收第二个中断的指示。

7. 发明授权

US08843730B2 Executing instruction packet with multiple instructions with same destination by performing logical operation on results of instructions and storing the result to the destination 有权
标题翻译：通过对指令结果执行逻辑运算并将结果存储到目的地，执行具有相同目的地的多个指令的指令包
公开(公告)号：US08843730B2
公开(公告)日：2014-09-23
申请号：US13228601
申请日：2011-09-09
申请人： Erich J. Plondke , Lucian Codrescu , Mao Zeng , Charles Joseph Tabony , Suresh K. Venkumahanti
发明人： Erich J. Plondke , Lucian Codrescu , Mao Zeng , Charles Joseph Tabony , Suresh K. Venkumahanti
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/38 , G06F9/30072 , G06F9/30094 , G06F9/3853
摘要： An apparatus includes a processor and a memory coupled to the processor. The memory stores an instruction packet (e.g., a VLIW instruction packet) including a first predicate independent instruction and a second predicate independent instruction. Each of the predicate independent instructions has the same destination.
摘要翻译：一种装置包括处理器和耦合到处理器的存储器。存储器存储包括第一谓词独立指令和第二谓词独立指令的指令分组（例如，VLIW指令分组）。每个谓词独立指令具有相同的目的地。

8. 发明授权

US08341353B2 System and method to access a portion of a level two memory and a level one memory 有权
标题翻译：用于访问二级存储器和一级存储器的一部分的系统和方法
公开(公告)号：US08341353B2
公开(公告)日：2012-12-25
申请号：US12687552
申请日：2010-01-14
申请人： Suresh K. Venkumahanti , Christopher Edward Koob , Lucian Codrescu
发明人： Suresh K. Venkumahanti , Christopher Edward Koob , Lucian Codrescu
IPC分类号： G06F12/08
CPC分类号： G06F12/0893 , G06F12/0811 , G06F12/0884
摘要： A system and method to access data from a portion of a level two memory or from a level one memory is disclosed. In a particular embodiment, the system includes a level one cache and a level two memory. A first portion of the level two memory is coupled to an input port and is addressable in parallel with the level one cache.
摘要翻译：公开了一种从二级存储器或一级存储器的一部分访问数据的系统和方法。在特定实施例中，系统包括一级缓存和二级存储器。二级存储器的第一部分耦合到输入端口，并且可与第一级缓存并行地寻址。

9. 发明授权

US07984281B2 Shared interrupt controller for a multi-threaded processor 有权
标题翻译：用于多线程处理器的共享中断控制器
公开(公告)号：US07984281B2
公开(公告)日：2011-07-19
申请号：US11954615
申请日：2007-12-12
申请人： Erich James Plondke , Lucian Codrescu , Muhammad Ahmed , William Anderson , Suresh K. Venkumahanti
发明人： Erich James Plondke , Lucian Codrescu , Muhammad Ahmed , William Anderson , Suresh K. Venkumahanti
IPC分类号： G06F9/00
CPC分类号： G06F9/4812 , G06F9/30123 , G06F9/3013 , G06F9/3851
摘要： A multi-threaded processor is disclosed that includes a sequencer adapted to provide instructions associated with one or more threads of a multi-threaded processor. The sequencer includes an interrupt controller adapted to receive one or more interrupts and to selectively allow a first thread of the one or more threads to service at least one interrupt. The interrupt controller includes logic to preclude a second thread of the one or more threads from responding to the at least one interrupt.
摘要翻译：公开了一种多线程处理器，其包括适于提供与多线程处理器的一个或多个线程相关联的指令的定序器。定序器包括适于接收一个或多个中断并且选择性地允许一个或多个线程的第一线程服务于至少一个中断的中断控制器。所述中断控制器包括排除所述一个或多个线程的第二线程以响应所述至少一个中断的逻辑。

10. 发明授权

US10025711B2 Hybrid write-through/write-back cache policy managers, and related systems and methods 有权
公开(公告)号：US10025711B2
公开(公告)日：2018-07-17
申请号：US13470643
申请日：2012-05-14
申请人： Peter G. Sassone , Christopher Edward Koob , Dana M. Vantrease , Suresh K. Venkumahanti , Lucian Codrescu
发明人： Peter G. Sassone , Christopher Edward Koob , Dana M. Vantrease , Suresh K. Venkumahanti , Lucian Codrescu
IPC分类号： G06F13/00 , G06F12/0804 , G06F1/32 , G06F12/0806 , G06F12/0846
摘要： Embodiments disclosed in the detailed description include hybrid write-through/write-back cache policy managers, and related systems and methods. A cache write policy manager is configured to determine whether at least two caches among a plurality of parallel caches are active. If all of one or more other caches are not active, the cache write policy manager is configured to instruct an active cache among the parallel caches to apply a write-hack cache policy. In this manner, the cache write policy manager may conserve power and/or increase performance of a singly active processor core. If any of the one or more other caches are active, the cache write policy manager is configured to instruct an active cache among the parallel caches to apply a write-through cache policy. In this manner, the cache write policy manager facilitates data coherency among the parallel caches when multiple processor cores are active.

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