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1. 发明申请

US20090124057A1 DAMASCENE GATE FIELD EFFECT TRANSISTOR WITH AN INTERNAL SPACER STRUCTURE 有权
标题翻译：具有内部间隔结构的大气门栅场效应晶体管
公开(公告)号：US20090124057A1
公开(公告)日：2009-05-14
申请号：US12354088
申请日：2009-01-15
申请人： Supratik Guha , Hussein I. Hanafi , Rajarao Jammy , Paul M. Solomon
发明人： Supratik Guha , Hussein I. Hanafi , Rajarao Jammy , Paul M. Solomon
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/2652 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28114 , H01L21/28194 , H01L21/28229 , H01L29/42376 , H01L29/4908 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/66553 , H01L29/66628 , H01L29/66772 , H01L29/78654
摘要： A MOSFET is disclosed that comprises a channel between a source extension and a drain extension, a dielectric layer over the channel, a gate spacer structure formed on a peripheral portion of the dielectric layer, and a gate formed on a non-peripheral portion of the dielectric layer, with at least a lower portion of the gate surrounded by and in contact with an internal surface of the gate spacer structure, and the gate is substantially aligned at its bottom with the channel. One method of forming the MOSFET comprises forming the dielectric layer, the gate spacer structure and the gate contact inside a cavity that has been formed by removing a sacrificial gate and spacer structure.
摘要翻译：公开了一种MOSFET，其包括在源极延伸部和漏极延伸部之间的沟道，沟道上的介电层，形成在电介质层的外围部分上的栅极间隔结构，以及形成在该介电层的非外围部分上的栅极电介质层，其栅极的至少一部分被栅极间隔结构的内表面包围并与栅极间隔结构的内表面接触，并且栅极在其底部基本上与沟道对准。形成MOSFET的一种方法包括在通过去除牺牲栅极和间隔物结构形成的空腔内部形成介电层，栅极间隔物结构和栅极接触。

2. 发明授权

US07479684B2 Field effect transistor including damascene gate with an internal spacer structure 失效
标题翻译：场效应晶体管包括具有内部间隔结构的镶嵌栅极
公开(公告)号：US07479684B2
公开(公告)日：2009-01-20
申请号：US10979633
申请日：2004-11-02
申请人： Supratik Guha , Hussein I. Hanafi , Rajarao Jammy , Paul M. Solomon
发明人： Supratik Guha , Hussein I. Hanafi , Rajarao Jammy , Paul M. Solomon
IPC分类号： H01L29/94
CPC分类号： H01L29/6656 , H01L21/2652 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28114 , H01L21/28194 , H01L21/28229 , H01L29/42376 , H01L29/4908 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/66553 , H01L29/66628 , H01L29/66772 , H01L29/78654
摘要： A MOSFET is disclosed that comprises a channel between a source extension and a drain extension, a dielectric layer over the channel, a gate spacer structure formed on a peripheral portion of the dielectric layer, and a gate formed on a non-peripheral portion of the dielectric layer, with at least a lower portion of the gate surrounded by and in contact with an internal surface of the gate spacer structure, and the gate is substantially aligned at its bottom with the channel.
摘要翻译：公开了一种MOSFET，其包括在源极延伸部和漏极延伸部之间的沟道，沟道上的介电层，形成在电介质层的外围部分上的栅极间隔结构，以及形成在该介电层的非外围部分上的栅极电介质层，其栅极的至少一部分被栅极间隔结构的内表面包围并与栅极间隔结构的内表面接触，并且栅极在其底部基本上与沟道对准。

3. 发明授权

US07723196B2 Damascene gate field effect transistor with an internal spacer structure 有权
标题翻译：具有内部间隔结构的镶嵌栅极场效应晶体管
公开(公告)号：US07723196B2
公开(公告)日：2010-05-25
申请号：US12354088
申请日：2009-01-15
申请人： Supratik Guha , Hussein I. Hanafi , Rajaroa Jammy , Paul M. Solomon
发明人： Supratik Guha , Hussein I. Hanafi , Rajaroa Jammy , Paul M. Solomon
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/2652 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28114 , H01L21/28194 , H01L21/28229 , H01L29/42376 , H01L29/4908 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/66553 , H01L29/66628 , H01L29/66772 , H01L29/78654
摘要： A MOSFET is disclosed that comprises a channel between a source extension and a drain extension, a dielectric layer over the channel, a gate spacer structure formed on a peripheral portion of the dielectric layer, and a gate formed on a non-peripheral portion of the dielectric layer, with at least a lower portion of the gate surrounded by and in contact with an internal surface of the gate spacer structure, and the gate is substantially aligned at its bottom with the channel. One method of forming the MOSFET comprises forming the dielectric layer, the gate spacer structure and the gate contact inside a cavity that has been formed by removing a sacrificial gate and spacer structure.
摘要翻译：公开了一种MOSFET，其包括在源极延伸部和漏极延伸部之间的沟道，沟道上的介电层，形成在电介质层的外围部分上的栅极间隔结构，以及形成在该介电层的非外围部分上的栅极电介质层，其栅极的至少一部分被栅极间隔结构的内表面包围并与栅极间隔结构的内表面接触，并且栅极在其底部基本上与沟道对准。形成MOSFET的一种方法包括在通过去除牺牲栅极和间隔物结构形成的空腔内部形成介电层，栅极间隔物结构和栅极接触。

4. 发明申请

US20080286930A1 NITRIDE-ENCAPSULATED FET (NNCFET) 失效
标题翻译：氮化物封装FET（NNCFET）
公开(公告)号：US20080286930A1
公开(公告)日：2008-11-20
申请号：US12142394
申请日：2008-06-19
申请人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
发明人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/78648
摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the silicon-containing channel layer to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further.
摘要翻译：提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。在本发明中，提供自对准隔离区以减小DGFET结构中的寄生电容。此外，本发明封装了含硅沟道层，使背栅能够被更大程度地氧化，从而进一步降低结构的寄生电容。

5. 发明授权

US07442612B2 Nitride-encapsulated FET (NNCFET) 有权
标题翻译：氮化物封装的FET（NNCFET）
公开(公告)号：US07442612B2
公开(公告)日：2008-10-28
申请号：US11481532
申请日：2006-07-06
申请人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
发明人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/78648
摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the silicon-containing channel layer to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further.
摘要翻译：提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。在本发明中，提供自对准隔离区以减小DGFET结构中的寄生电容。此外，本发明封装了含硅沟道层，使背栅能够被更大程度地氧化，从而进一步降低结构的寄生电容。

6. 发明授权

US07648880B2 Nitride-encapsulated FET (NNCFET) 失效
标题翻译：氮化物封装的FET（NNCFET）
公开(公告)号：US07648880B2
公开(公告)日：2010-01-19
申请号：US12142394
申请日：2008-06-19
申请人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
发明人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/78648
摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the silicon-containing channel layer to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further.
摘要翻译：提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。在本发明中，提供自对准隔离区以减小DGFET结构中的寄生电容。此外，本发明封装了含硅沟道层，使背栅能够被更大程度地氧化，从而进一步降低结构的寄生电容。

7. 发明授权

US07078773B2 Nitride-encapsulated FET (NNCFET) 失效
标题翻译：氮化物封装的FET（NNCFET）
公开(公告)号：US07078773B2
公开(公告)日：2006-07-18
申请号：US10328258
申请日：2002-12-23
申请人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
发明人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66772 , H01L29/78648
摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the silicon-containing channel layer to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further.
摘要翻译：提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。在本发明中，提供自对准隔离区以减小DGFET结构中的寄生电容。此外，本发明封装了含硅沟道层，使背栅能够被更大程度地氧化，从而进一步降低结构的寄生电容。

8. 发明授权

US07934181B2 Method and apparatus for improving SRAM cell stability by using boosted word lines 有权
标题翻译：通过使用升压字线来提高SRAM单元稳定性的方法和装置
公开(公告)号：US07934181B2
公开(公告)日：2011-04-26
申请号：US12130472
申请日：2008-05-30
申请人： Hussein I. Hanafi , Richard Q. Williams
发明人： Hussein I. Hanafi , Richard Q. Williams
IPC分类号： G06F17/50 , G11C16/06 , G11C7/00 , G11C8/00
CPC分类号： G11C7/02 , G11C8/08 , G11C11/413
摘要： The present invention relates to methods and apparatus for improving the stability of static random access memory (SRAM) cells by using boosted word lines. Specifically, a boosted word line voltage (Vdd′) is applied to the word line of a selected SRAM cell, while such a boosted word line voltage (Vdd′) is sufficiently higher than the power supply voltage (Vdd) of the SRAM cell so as to improve the cell stability to a desired level. Specifically, a specific boosted word line voltage is predetermined for each SRAM cell based on the specific cell configuration, by using a circuit simulation program, such as the BERKELEY-SPICE simulation program. A boost voltage generator is then used to apply the predetermined boosted word line voltage to the selected SRAM cell.
摘要翻译：本发明涉及通过使用增强字线来提高静态随机存取存储器（SRAM）单元的稳定性的方法和装置。具体地说，将升压的字线电压（Vdd'）施加到所选择的SRAM单元的字线，而这样的升压字线电压（Vdd'）比SRAM单元的电源电压（Vdd）充分高以将细胞稳定性提高到所需水平。具体地，通过使用例如BERKELEY-SPICE仿真程序的电路仿真程序，基于特定单元配置为每个SRAM单元预定特定的升压字线电压。然后使用升压电压发生器将预定的升压字线电压施加到所选择的SRAM单元。

9. 发明申请

US20100188889A1 BACK GATED SRAM CELL 有权
公开(公告)号：US20100188889A1
公开(公告)日：2010-07-29
申请号：US12752286
申请日：2010-04-01
申请人： Hussein I. Hanafi
发明人： Hussein I. Hanafi
IPC分类号： G11C11/00
CPC分类号： H01L27/1108 , G11C11/412 , G11C11/413 , H01L29/785
摘要： Methods, devices and systems for a back gated static random access memory (SRAM) cell are provided. One method embodiment for operating an SRAM cell includes applying a potential to a back gate of a pair of cross coupled p-type pull up transistors in the SRAM during a write operation. The method includes applying a ground to the back gate of the pair of cross coupled p-type pull up transistors during a read operation. The charge stored on a pair of cross coupled storage nodes of the SRAM is coupled to a front gate and a back gate of a pair of cross coupled n-type pull down transistors in the SRAM during the write operation and during a read operation.
摘要翻译：提供了用于后门控静态随机存取存储器（SRAM）单元的方法，装置和系统。用于操作SRAM单元的一个方法实施例包括在写入操作期间将电位施加到SRAM中的一对交叉耦合p型上拉晶体管的背栅极。该方法包括在读取操作期间将接地施加到该对交叉耦合p型上拉晶体管的背栅极。存储在SRAM的一对交叉耦合的存储节点上的电荷在写入操作期间和在读取操作期间耦合到SRAM中的一对交叉耦合的n型下拉晶体管的前栅极和后栅极。

10. 发明授权

US07732286B2 Buried biasing wells in FETs (Field Effect Transistors) 有权
标题翻译： FET中的埋置偏置阱（场效应晶体管）
公开(公告)号：US07732286B2
公开(公告)日：2010-06-08
申请号：US11845244
申请日：2007-08-27
申请人： Hussein I. Hanafi , Edward J. Nowak
发明人： Hussein I. Hanafi , Edward J. Nowak
IPC分类号： H01L21/336
CPC分类号： H01L29/105 , H01L29/0653 , H01L29/66628 , H01L29/7834
摘要： A method for fabricating a semiconductor structure. The semiconductor structure comprises first and second source/drain regions; a channel region disposed between the first and second source/drain regions; a buried well region in physical contact with the channel region; and a buried barrier region being disposed between the buried well region and the first source/drain region and being disposed between the buried well region and the second source/drain region, wherein the buried barrier region is adapted for preventing current leakage and dopant diffusion between the buried well region and the first source/drain region and between the buried well region and the second source/drain region.
摘要翻译：一种半导体结构的制造方法。半导体结构包括第一和第二源极/漏极区域; 设置在所述第一和第二源极/漏极区之间的沟道区; 与通道区域物理接触的掩埋阱区域; 并且埋置的阻挡区域设置在所述掩埋阱区域和所述第一源极/漏极区域之间并且设置在所述掩埋阱区域和所述第二源极/漏极区域之间，其中所述掩埋势垒区域适于防止所述掩埋阻挡区域之间的电流泄漏和掺杂剂扩散埋入阱区域和第一源极/漏极区域以及掩埋阱区域和第二源极/漏极区域之间。

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