专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08762915B1 System and method for integrated circuit die size reduction 有权
标题翻译：集成电路芯片尺寸缩小的系统和方法
公开(公告)号：US08762915B1
公开(公告)日：2014-06-24
申请号：US12884264
申请日：2010-09-17
申请人： Balaji Prabhakar , Sunil Kumar Singla
发明人： Balaji Prabhakar , Sunil Kumar Singla
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A circuit analysis tool is provided for die size reduction analysis. A processor determines a first initial output slack time. If the first initial output slack time is greater than zero, a first circuit element is modeled with a second die area, less than the first die area. The second die area is associated with a third delay greater than the first delay. Then, the second data signal is modeled equal to the first data signal with the third delay. If a first modified output slack time is greater than or equal to zero, the first circuit element first die can be replaced with the second die. If the first modified output slack time is a first value less than zero, a first delay is added to the clock signal that is greater than or equal to the first value.
摘要翻译：提供了一种电路分析工具用于模具尺寸缩小分析。处理器确定第一初始输出松弛时间。如果第一初始输出松弛时间大于零，则第一电路元件被建模为具有小于第一管芯区域的第二管芯区域。第二管芯区域与大于第一延迟的第三延迟相关联。然后，第二数据信号被建模为等于具有第三延迟的第一数据信号。如果第一修改的输出松弛时间大于或等于零，则可以用第二管芯替换第一电路元件第一管芯。如果第一修改的输出松弛时间是小于零的第一值，则将第一延迟添加到大于或等于第一值的时钟信号。

2. 发明授权

US08539413B1 Frequency optimization using useful skew timing 有权
标题翻译：使用有用的偏移时序进行频率优化
公开(公告)号：US08539413B1
公开(公告)日：2013-09-17
申请号：US12767894
申请日：2010-04-27
申请人： Sunil Kumar Singla , Balaji Prabhakar
发明人： Sunil Kumar Singla , Balaji Prabhakar
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A circuit analysis tool is provided for optimizing circuit clock operating frequency using useful skew timing analysis. The instructions supply clock signal with an optimized operating frequency. A first gate signal input slack time is determined with respect to the clock signal to the first gate. If the first gate signal input has a negative slack time, a delay is added to the first clock signal. A second gate signal input slack time is determined with respect to the clock signal to the second gate. If the second gate signal input slack time is negative, a delay is added to the second clock signal necessary to create a second gate signal input positive slack time. In response to the first and second gate signal input positive slack times, it is determined that the circuit successfully operates at the clock optimized operating frequency.
摘要翻译：提供电路分析工具，用于使用有用的偏转时序分析来优化电路时钟工作频率。指令提供具有优化工作频率的时钟信号。相对于到第一门的时钟信号确定第一门信号输入松弛时间。如果第一门信号输入具有负的松弛时间，则延迟被添加到第一时钟信号。相对于到第二门的时钟信号确定第二门信号输入松弛时间。如果第二门信号输入松弛时间为负，则将延迟添加到产生第二门信号输入正松弛时间所必需的第二时钟信号。响应于第一和第二门信号输入正的松弛时间，确定电路在时钟优化的工作频率下成功地工作。

3. 发明授权

US08868956B1 System-on-chip with feedback loop for processor frequency control 有权
标题翻译：具有用于处理器频率控制的反馈回路的片上系统
公开(公告)号：US08868956B1
公开(公告)日：2014-10-21
申请号：US12639064
申请日：2009-12-16
申请人： Waseem Saify Kraipak , Pradeep Dharane , Yoon Sang Chae , Sunil Kumar Singla
发明人： Waseem Saify Kraipak , Pradeep Dharane , Yoon Sang Chae , Sunil Kumar Singla
IPC分类号： G06F1/26 , G06F1/28 , G06F1/30
CPC分类号： G06F1/26 , G06F1/3203 , Y02D10/126
摘要： A system and method are provided for using feedback to control processor frequencies in a system-on-chip (SoC). The method is associated with an SoC having a processor operating frequency responsive to a processor supply voltage on a first SOC interface, and a controller for managing the operating frequency. The controller accepts a frequency selection command associated with a first operating frequency, at a second SoC interface. The controller sends a first voltage command associated with the first frequency, via a third SOC interface, to a voltage regulator supplying the processor supply voltage. Then, the controller monitors the processor supply voltage. In response to detecting a processor first supply voltage, the processor is enabled to operate at the first frequency.
摘要翻译：提供了一种系统和方法，用于使用反馈来控制片上系统（SoC）中的处理器频率。该方法与具有响应于第一SOC接口上的处理器电源电压的处理器工作频率的SoC和用于管理工作频率的控制器相关联。控制器在第二SoC接口处接受与第一工作频率相关联的频率选择命令。控制器经由第三SOC接口将与第一频率相关联的第一电压命令发送到提供处理器电源电压的电压调节器。然后，控制器监视处理器电源电压。响应于检测到处理器的第一电源电压，处理器能够以第一频率工作。

4. 发明授权

US08205181B1 Victim net crosstalk reduction 有权
标题翻译：受害者网络串扰减少
公开(公告)号：US08205181B1
公开(公告)日：2012-06-19
申请号：US12718624
申请日：2010-03-05
申请人： Sunil Kumar Singla , Sudhir Koul
发明人： Sunil Kumar Singla , Sudhir Koul
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F2217/82 , G06F2217/84
摘要： A circuit analysis tool is provided, enabled with software instructions, for minimizing circuit crosstalk. The instructions provide a first circuit connected to an output mode, having a last gate with a plurality of inputs and an output. The instructions calculate a first circuit victim net delay range (timing window) having a minimum delay (Vmin) and a maximum delay (Vmax). A second circuit is provided having an output connected to the output node to supply an aggressor net delay range (A1) having a minimum delay (A1min) and a maximum delay (A1max). The aggressor net delay range at least partially overlaps the victim net delay range. Without increasing the value of Vmax (critical path timing), the first circuit victim net delay range is shrunk, thereby minimizing crosstalk between the first and second circuits without an increase in first circuit maximum signal delay.
摘要翻译：提供了一个电路分析工具，使软件指令能够最小化电路串扰。指令提供连接到输出模式的第一电路，具有具有多个输入和输出的最后一个门。指令计算具有最小延迟（Vmin）和最大延迟（Vmax）的第一电路受害者净延迟范围（定时窗口）。提供第二电路，其具有连接到输出节点的输出，以提供具有最小延迟（A1min）和最大延迟（A1max）的侵略者净延迟范围（A1）。侵略者净延迟范围至少部分地与受害者净延迟范围重叠。在不增加Vmax（关键路径定时）的值的情况下，第一电路受害网络延迟范围被缩小，从而最小化第一和第二电路之间的串扰，而不增加第一电路最大信号延迟。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式