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1. 发明授权

US08927366B2 Method of manufacturing a non-volatile memory device having a vertical structure 有权
标题翻译：制造具有垂直结构的非易失性存储器件的方法
公开(公告)号：US08927366B2
公开(公告)日：2015-01-06
申请号：US13610344
申请日：2012-09-11
申请人： Sung-hae Lee , Ki-hyun Hwang , Jin-gyun Kim
发明人： Sung-hae Lee , Ki-hyun Hwang , Jin-gyun Kim
IPC分类号： H01L21/04 , H01L27/115
CPC分类号： H01L27/11556 , H01L27/11582
摘要： A method of manufacturing a non-volatile memory device, wherein the method includes: alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate; forming a plurality of first openings that pass through the interlayer sacrificial layers and the interlayer insulating layers to expose a first portion of the substrate; forming a semiconductor region on a side wall and a lower surface of each of the first openings; forming an embedded insulating layer in each of the first openings; forming a first conductive layer on the embedded insulating layer inside each of the first openings; forming a second opening exposing a second portion of the substrate and forming an impurity region on the second portion; forming a metal layer to cover the first conductive layer and the impurity region; and forming the metal layer into a metal silicide layer.
摘要翻译：一种制造非易失性存储器件的方法，其中所述方法包括：在衬底上交替层叠层间牺牲层和层间绝缘层; 形成穿过所述层间牺牲层和所述层间绝缘层的多个第一开口，以露出所述衬底的第一部分; 在每个所述第一开口的侧壁和下表面上形成半导体区域; 在每个所述第一开口中形成嵌入绝缘层; 在每个所述第一开口内的所述嵌入式绝缘层上形成第一导电层; 形成露出所述衬底的第二部分并在所述第二部分上形成杂质区的第二开口; 形成覆盖所述第一导电层和所述杂质区域的金属层; 以及将所述金属层形成为金属硅化物层。

2. 发明申请

US20130089974A1 METHOD OF MANUFACTURING A NON-VOLATILE MEMORY DEVICE HAVING A VERTICAL STRUCTURE 有权
标题翻译：制造具有垂直结构的非易失性存储器件的方法
公开(公告)号：US20130089974A1
公开(公告)日：2013-04-11
申请号：US13610344
申请日：2012-09-11
申请人： Sung-hae Lee , Ki-hyun Hwang , Jin-gyun Kim
发明人： Sung-hae Lee , Ki-hyun Hwang , Jin-gyun Kim
IPC分类号： H01L21/04
CPC分类号： H01L27/11556 , H01L27/11582
摘要： A method of manufacturing a non-volatile memory device, wherein the method includes: alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate; forming a plurality of first openings that pass through the interlayer sacrificial layers and the interlayer insulating layers to expose a first portion of the substrate; forming a semiconductor region on a side wall and a lower surface of each of the first openings; forming an embedded insulating layer in each of the first openings; forming a first conductive layer on the embedded insulating layer inside each of the first openings; forming a second opening exposing a second portion of the substrate and forming an impurity region on the second portion; forming a metal layer to cover the first conductive layer and the impurity region; and forming the metal layer into a metal silicide layer.
摘要翻译：一种制造非易失性存储器件的方法，其中所述方法包括：在衬底上交替层叠层间牺牲层和层间绝缘层; 形成穿过所述层间牺牲层和所述层间绝缘层的多个第一开口，以露出所述衬底的第一部分; 在每个所述第一开口的侧壁和下表面上形成半导体区域; 在每个所述第一开口中形成嵌入绝缘层; 在每个所述第一开口内的所述嵌入式绝缘层上形成第一导电层; 形成露出所述衬底的第二部分并在所述第二部分上形成杂质区的第二开口; 形成覆盖所述第一导电层和所述杂质区域的金属层; 以及将所述金属层形成为金属硅化物层。

3. 发明申请

US20070111545A1 Methods of forming silicon dioxide layers using atomic layer deposition 审中-公开
标题翻译：使用原子层沉积法形成二氧化硅层的方法
公开(公告)号：US20070111545A1
公开(公告)日：2007-05-17
申请号：US11521145
申请日：2006-09-14
申请人： Sung-hae Lee , Ki-hyun Hwang , Jin-gyun Kim , Sang-ryol Yang , Hong-suk Kim , Jin-tae Noh
发明人： Sung-hae Lee , Ki-hyun Hwang , Jin-gyun Kim , Sang-ryol Yang , Hong-suk Kim , Jin-tae Noh
IPC分类号： H01L21/31
CPC分类号： H01L21/3141 , C23C16/401 , C23C16/452 , C23C16/45525 , C23C16/45542 , H01L21/02164 , H01L21/02208 , H01L21/02274 , H01L21/0228 , H01L21/31612
摘要： Provided herein are methods of forming a silicon dioxide layer on a substrate using an atomic layer deposition (ALD) method that include supplying a Si precursor to the substrate and forming on the substrate a Si layer including at least one Si atomic layer; and (b) supplying an oxygen radical to the Si layer to replace at least one Si—Si bond within the Si layer with a Si—O bond, thereby oxidizing the Si layer, to form a silicon dioxide layer on the substrate.
摘要翻译：本文提供了使用原子层沉积（ALD）方法在衬底上形成二氧化硅层的方法，其包括向衬底提供Si前体并在衬底上形成包含至少一个Si原子层的Si层; 和（b）向Si层提供氧自由基以用Si-O键代替Si层内的至少一个Si-Si键，从而氧化Si层，以在衬底上形成二氧化硅层。

4. 发明申请

US20090085160A1 Semiconductor Device Including Insulating Layer of Cubic System or Tetragonal System 有权
标题翻译：包括立方体或四边形系统的绝缘层的半导体器件
公开(公告)号：US20090085160A1
公开(公告)日：2009-04-02
申请号：US12238822
申请日：2008-09-26
申请人： Jong-cheol Lee , Jun-noh Lee , Ki-vin Im , Ki-yeon Park , Sung-hae Lee , Sang-yeol Kang
发明人： Jong-cheol Lee , Jun-noh Lee , Ki-vin Im , Ki-yeon Park , Sung-hae Lee , Sang-yeol Kang
IPC分类号： H01L29/92
CPC分类号： H01L29/51 , H01L21/28273 , H01L21/28282 , H01L21/31641 , H01L21/31645 , H01L27/10852 , H01L28/65 , H01L29/513
摘要： Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.
摘要翻译：本发明提供一种半导体器件，其具有立方晶系或四方晶系的绝缘层，具有良好的电特性。半导体器件包括：半导体衬底，包括有源区，形成在半导体衬底的有源区中的晶体管，形成在半导体衬底上的层间绝缘层和形成在层间绝缘层中的接触插塞;以及其电连接到晶体管。半导体器件可以包括形成在层间绝缘层上并且与电性连接的接触插塞的下电极，形成在下电极上的上电极和立方体系的绝缘层或包括金属硅酸盐层。绝缘层可以形成在下电极和上电极之间。

5. 发明申请

US20120168904A1 Semiconductor Device Including Insulating Layer of Cubic System or Tetragonal System 有权
标题翻译：包括立方体或四边形系统的绝缘层的半导体器件
公开(公告)号：US20120168904A1
公开(公告)日：2012-07-05
申请号：US13418472
申请日：2012-03-13
申请人： Jong-cheol Lee , Jun-noh Lee , Ki-vin Im , Ki-yeon Park , Sung-hae Lee , Sang-yeol Kang
发明人： Jong-cheol Lee , Jun-noh Lee , Ki-vin Im , Ki-yeon Park , Sung-hae Lee , Sang-yeol Kang
IPC分类号： H01L29/92
CPC分类号： H01L29/51 , H01L21/28273 , H01L21/28282 , H01L21/31641 , H01L21/31645 , H01L27/10852 , H01L28/65 , H01L29/513
摘要： Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.
摘要翻译：本发明提供一种半导体器件，其具有立方晶系或四方晶系的绝缘层，具有良好的电特性。半导体器件包括：半导体衬底，包括有源区，形成在半导体衬底的有源区中的晶体管，形成在半导体衬底上的层间绝缘层和形成在层间绝缘层中的接触插塞;以及其电连接到晶体管。半导体器件可以包括形成在层间绝缘层上并且与电性连接的接触插塞的下电极，形成在下电极上的上电极和立方体系的绝缘层或包括金属硅酸盐层。绝缘层可以形成在下电极和上电极之间。

6. 发明授权

US08159012B2 Semiconductor device including insulating layer of cubic system or tetragonal system 有权
标题翻译：半导体器件包括立方体或四方晶系的绝缘层
公开(公告)号：US08159012B2
公开(公告)日：2012-04-17
申请号：US12238822
申请日：2008-09-26
申请人： Jong-cheol Lee , Jun-noh Lee , Ki-vin Im , Ki-yeon Park , Sung-hae Lee , Sang-yeol Kang
发明人： Jong-cheol Lee , Jun-noh Lee , Ki-vin Im , Ki-yeon Park , Sung-hae Lee , Sang-yeol Kang
IPC分类号： H01L27/108
CPC分类号： H01L29/51 , H01L21/28273 , H01L21/28282 , H01L21/31641 , H01L21/31645 , H01L27/10852 , H01L28/65 , H01L29/513
摘要： Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.
摘要翻译：本发明提供一种半导体器件，其具有立方晶系或四方晶系的绝缘层，具有良好的电特性。半导体器件包括：半导体衬底，包括有源区，形成在半导体衬底的有源区中的晶体管，形成在半导体衬底上的层间绝缘层和形成在层间绝缘层中的接触插塞;以及其电连接到晶体管。半导体器件可以包括形成在层间绝缘层上并且与电性连接的接触插塞的下电极，形成在下电极上的上电极和立方体系的绝缘层或包括金属硅酸盐层。绝缘层可以形成在下电极和上电极之间。

7. 发明授权

US08710564B2 Semiconductor device including insulating layer of cubic system or tetragonal system 有权
标题翻译：半导体器件包括立方体或四方晶系的绝缘层
公开(公告)号：US08710564B2
公开(公告)日：2014-04-29
申请号：US13418472
申请日：2012-03-13
申请人： Jong-cheol Lee , Jun-noh Lee , Ki-vin Im , Ki-yeon Park , Sung-hae Lee , Sang-yeol Kang
发明人： Jong-cheol Lee , Jun-noh Lee , Ki-vin Im , Ki-yeon Park , Sung-hae Lee , Sang-yeol Kang
IPC分类号： H01L27/108
CPC分类号： H01L29/51 , H01L21/28273 , H01L21/28282 , H01L21/31641 , H01L21/31645 , H01L27/10852 , H01L28/65 , H01L29/513
摘要： Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.
摘要翻译：本发明提供一种半导体器件，其具有立方晶系或四方晶系的绝缘层，具有良好的电特性。半导体器件包括：半导体衬底，包括有源区，形成在半导体衬底的有源区中的晶体管，形成在半导体衬底上的层间绝缘层和形成在层间绝缘层中的接触插塞;以及其电连接到晶体管。半导体器件可以包括形成在层间绝缘层上并且与电性连接的接触插塞的下电极，形成在下电极上的上电极和立方体系的绝缘层或包括金属硅酸盐层。绝缘层可以形成在下电极和上电极之间。

8. 发明授权

US07800162B2 Nonvolatile memory device and method of fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07800162B2
公开(公告)日：2010-09-21
申请号：US12235689
申请日：2008-09-23
申请人： Sung-hae Lee , Ki-yeon Park , Min-Kyung Ryu , Myoung-bum Lee , Jun-noh Lee
发明人： Sung-hae Lee , Ki-yeon Park , Min-Kyung Ryu , Myoung-bum Lee , Jun-noh Lee
IPC分类号： H01L29/94
CPC分类号： H01L29/42324 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L29/4234 , H01L29/513 , H01L29/7881 , H01L29/792
摘要： A nonvolatile memory device includes a semiconductor substrate, a tunneling insulation layer on the semiconductor substrate, a charge storage layer on the tunneling insulation layer, an inter-electrode insulation layer on the charge storage layer, and a control gate electrode on the inter-electrode insulation layer. The inter-electrode insulation layer includes a high-k dielectric layer having a dielectric constant greater than that of a silicon nitride, and an interfacial layer between the charge storage layer and the high-k dielectric layer. The interfacial layer includes a silicon oxynitride layer.
摘要翻译：非易失性存储器件包括半导体衬底，半导体衬底上的隧道绝缘层，隧道绝缘层上的电荷存储层，电荷存储层上的电极间绝缘层和电极上的控制栅电极绝缘层。电极间绝缘层包括具有大于氮化硅的介电常数的高k电介质层，以及电荷存储层和高k电介质层之间的界面层。界面层包括氧氮化硅层。

9. 发明申请

US20090127611A1 NON-VOLATILE MEMORY DEVICE AND MEMORY CARD AND SYSTEM INCLUDING THE SAME 审中-公开
标题翻译：非易失性存储器件和包括其的存储卡和系统
公开(公告)号：US20090127611A1
公开(公告)日：2009-05-21
申请号：US12120443
申请日：2008-05-14
申请人： Ki-yeon Park , Cha-young Yoo , Sung-hae Lee , Jun-noh Lee , Min-kyung Ryu
发明人： Ki-yeon Park , Cha-young Yoo , Sung-hae Lee , Jun-noh Lee , Min-kyung Ryu
IPC分类号： H01L29/792 , H01L29/788
CPC分类号： H01L29/513 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/4234
摘要： A non-volatile memory device includes a semiconductor layer including source and drain regions and a channel region between the source and drain regions; a tunneling insulating layer on the channel region of the semiconductor layer; a charge storage layer on the tunneling insulating layer; a blocking insulating layer on the charge storage layer and including a first oxide layer with a first thickness, a high-k dielectric layer, and a second oxide layer with a second thickness different from the first thickness that are stacked sequentially on the charge storage layer; and a control gate on the blocking insulating layer.
摘要翻译：非易失性存储器件包括包括源区和漏区的半导体层和源区和漏区之间的沟道区; 在半导体层的沟道区上的隧道绝缘层; 隧道绝缘层上的电荷存储层; 电荷存储层上的阻挡绝缘层，并且包括具有第一厚度的第一氧化物层，高k电介质层和具有不同于第一厚度的第二厚度的第二氧化物层，其顺次层叠在电荷存储层上 ; 和阻挡绝缘层上的控制栅极。

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