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1. 发明申请

US20120300561A1 MEMORY DEVICES AND PROGRAM METHODS THEREOF 有权
标题翻译：存储器件及其程序方法
公开(公告)号：US20120300561A1
公开(公告)日：2012-11-29
申请号：US13476196
申请日：2012-05-21
申请人： Sung-Won YUN , ChiWeon YOON , Kyung-Hwa KANG , JinTae KIM
发明人： Sung-Won YUN , ChiWeon YOON , Kyung-Hwa KANG , JinTae KIM
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C5/025 , G11C5/145 , G11C8/08 , G11C8/14 , G11C16/0483 , G11C16/12 , G11C16/30
摘要： Memory devices and program methods thereof, the memory devices including a memory cell array with a three-dimensional structure, a voltage generator configured to supply a pass voltage and a program voltage to the memory cell array, and a control logic configured to make the rising slope of the pass voltage variable with a program loop during a program operation. The memory device may improve a program speed by adjusting the rising slope of the pass voltage according to the program loop.
摘要翻译：存储器件及其编程方法，所述存储器件包括具有三维结构的存储单元阵列，被配置为向所述存储单元阵列提供通过电压和编程电压的电压发生器，以及配置为使所述上升的控制逻辑程序运行期间程序循环的通过电压变量的斜率。存储器件可以通过根据程序循环调整通过电压的上升沿来提高编程速度。

2. 发明申请

US20120201080A1 Nonvolatile Memory Devices And Driving Methods Thereof 有权
标题翻译：非易失存储器件及其驱动方法
公开(公告)号：US20120201080A1
公开(公告)日：2012-08-09
申请号：US13368769
申请日：2012-02-08
申请人： Kyung-Hwa KANG , Sang-Wan NAM , Donghyuk CHAE , ChiWeon YOON
发明人： Kyung-Hwa KANG , Sang-Wan NAM , Donghyuk CHAE , ChiWeon YOON
IPC分类号： G11C16/04 , G11C16/06 , G11C16/08
CPC分类号： G11C16/0483 , G11C16/0466 , G11C16/08 , G11C16/24 , H01L23/528 , H01L27/11565 , H01L27/1157 , H01L27/11582
摘要： Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.
摘要翻译：非易失性存储器件包括具有连接在衬底和多个位线之间并由选择线选择的多个单元串的存储单元阵列，以及配置成在至少两个方向上驱动选择线的选通电路。

3. 发明申请

US20160254054A1 NONVOLATILE MEMORY DEVICES AND DRIVING METHODS THEREOF 审中-公开
公开(公告)号：US20160254054A1
公开(公告)日：2016-09-01
申请号：US15152692
申请日：2016-05-12
申请人： Kyung-Hwa KANG , Sang-Wan NAM , Donghyuk CHAE , ChiWeon YOON
发明人： Kyung-Hwa KANG , Sang-Wan NAM , Donghyuk CHAE , ChiWeon YOON
IPC分类号： G11C16/04 , H01L27/115 , H01L23/528 , G11C16/24 , G11C16/08
CPC分类号： G11C16/0483 , G11C16/0466 , G11C16/08 , G11C16/24 , H01L23/528 , H01L27/11565 , H01L27/1157 , H01L27/11582
摘要： Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.

4. 发明申请

US20130170297A1 NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权
标题翻译：非易失性存储器件和包括其的存储器系统
公开(公告)号：US20130170297A1
公开(公告)日：2013-07-04
申请号：US13619118
申请日：2012-09-14
申请人： Sang-Wan NAM , Kyung-Hwa KANG , Junghoon PARK
发明人： Sang-Wan NAM , Kyung-Hwa KANG , Junghoon PARK
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/08 , G11C16/10 , H01L27/115 , H01L27/11582
摘要： According to example embodiments, a nonvolatile memory device includes a first and a second NAND string. The first NAND string includes a first string selection transistor, a first local ground and a first global ground selection transistor, and first memory cells stacked in a direction perpendicular to a substrate. The second NAND string includes a second string selection transistor, a second local ground and a second global ground selection transistor, and second memory cells stacked in the direction perpendicular to the substrate. The device includes a selection line driver including path transistors configured to select and provide at least one operation voltage to the first and second string selection transistors, the first and second local and global ground selection transistors. The first and second string selection transistors are electrically isolated from each other, and the first and second global ground selection transistors are electrically connected.
摘要翻译：根据示例性实施例，非易失性存储器件包括第一和第二NAND串。第一NAND串包括第一串选择晶体管，第一局部地和第一全局接地选择晶体管，以及沿垂直于衬底的方向堆叠的第一存储单元。第二NAND串包括第二串选择晶体管，第二局部地和第二全局接地选择晶体管，以及沿与基板垂直的方向堆叠的第二存储单元。该器件包括选择线驱动器，其包括被配置为选择并向第一和第二串选择晶体管，第一和第二局部和全局地选择晶体管提供至少一个操作电压的路径晶体管。第一和第二串选择晶体管彼此电绝缘，并且第一和第二全局接地选择晶体管电连接。

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