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    • 7. 发明授权
    • Gate driver and display apparatus having the same
    • 门驱动器和显示装置具有相同的功能
    • US08194026B2
    • 2012-06-05
    • US11782957
    • 2007-07-25
    • Hong-Woo LeeMyung-Koo HurJong-Hwan LeeBeom-Jun KimSung-Man Kim
    • Hong-Woo LeeMyung-Koo HurJong-Hwan LeeBeom-Jun KimSung-Man Kim
    • G09G3/36
    • G09G3/3677G09G2300/0408G09G2310/0267G09G2320/02G09G2330/08G11C19/28
    • A gate driver comprises a shift register that has a plurality of stages connected together and outputs a gate signal comprising a first pulse and a second pulse to a gate line. A stage includes a holding part, a pre-charging part, a pull-up part, and a pull-down part. The holding part discharges an output terminal to an off-voltage in response to a first clock signal. The pre-charging part turns off the holding part and outputs the first clock signal as the first pulse to the output terminal in response to an output signal of a previous stage. The pull-up part outputs a second clock signal as the second pulse to the output terminal in response to the output signal of the previous stage. The pull-down part discharges the first output terminal to the off-voltage in response to an output signal of a next stage.
    • 栅极驱动器包括具有连接在一起的多个级的移位寄存器,并将包括第一脉冲和第二脉冲的门信号输出到栅极线。 舞台包括保持部分,预充电部分,上拉部分和下拉部分。 保持部分响应于第一时钟信号将输出端子放电到截止电压。 预充电部件关闭保持部件,并响应于前一级的输出信号将第一时钟信号作为第一脉冲输出到输出端子。 上拉部分响应于前一级的输出信号,将第二时钟信号作为第二脉冲输出到输出端。 下拉部分响应于下一级的输出信号将第一输出端子放电到截止电压。
    • 8. 发明授权
    • Gate driving circuit and display apparatus having the same
    • 栅极驱动电路及其显示装置
    • US08098227B2
    • 2012-01-17
    • US12338182
    • 2008-12-18
    • Hong-Woo LeeJong-Hwan LeeBeom-Jun KimSung-Man KimGyu-Tae KimKyoung-Jun Jang
    • Hong-Woo LeeJong-Hwan LeeBeom-Jun KimSung-Man KimGyu-Tae KimKyoung-Jun Jang
    • G09G3/36
    • G09G3/3677G11C19/184H03K17/165
    • A gate driving circuit includes cascaded stages, each including a pull-up part, a carry part, a pull-up driving part, a holding part and an inverter. The pull-up part pulls up a gate voltage to an input clock. The carry part pulls up a carry voltage to the input clock. The pull-up driving part is connected to a control terminal (Q-node) common to the carry part and the pull-up part, and receives a previous carry voltage from a previous stage to turn on the pull-up part and the carry part. The holding part holds the gate voltage at an off-voltage, and the inverter controls at least one of turning on the holding part and turning off the holding part based on an inverter clock. A high level of the inverter clock in a given horizontal period (1H) temporally precedes a high level of the input clock by a predetermined time interval.
    • 栅极驱动电路包括级联级,每级包括上拉部分,进位部分,上拉驱动部分,保持部分和逆变器。 上拉部分将输入时钟的栅极电压上拉。 进位部分将输入电压提升到输入时钟。 上拉驱动部分连接到与进位部分和上拉部分相同的控制端子(Q-节点),并且从前一级接收先前的进位电压以打开上拉部分和进位 部分。 保持部将栅极电压保持在截止电压,逆变器基于逆变器时钟来控制保持部的开启和关闭保持部中的至少一个。 给定水平周期(1H)中的高电平的反相器时钟在时间上在预定时间间隔的输入时钟的高电平之前。