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    • 1. 发明授权
    • Signal line structure of a flat display
    • 平面显示器的信号线结构
    • US09182641B2
    • 2015-11-10
    • US13166826
    • 2011-06-23
    • Wei-Chou LanSung-Hui HuangChia-Chun YehTed-Hong Shinn
    • Wei-Chou LanSung-Hui HuangChia-Chun YehTed-Hong Shinn
    • H01L23/48H01L23/52H01L29/40G02F1/1362G09G3/20H01L27/12
    • G02F1/136286G02F2001/13629G09G3/20G09G2300/0421H01L27/124
    • The signal line structure is disposed between a gate driver and a display area of a display. The signal line structure includes a substrate, first metal layers, a first insulation layer, second metal layers, a second insulation layer and third metal layers. The first metal layers are arranged in parallel and toward a first direction in the substrate. The first insulation layer is disposed in the substrate and covers the first metal layers. The second metal layers are disposed on the positions of the first insulation layer corresponding to the first metal layers. The second insulation layer is disposed on the second metal layers and the first insulation layer. The third metal layers are disposed on the positions corresponding to the second metal layers in the second insulation layer. The distance between two adjacent second metal layers is less than that between two adjacent first metal layers.
    • 信号线结构设置在显示器的栅极驱动器和显示区域之间。 信号线结构包括基板,第一金属层,第一绝缘层,第二金属层,第二绝缘层和第三金属层。 第一金属层在基板中平行且朝向第一方向排列。 第一绝缘层设置在基板中并覆盖第一金属层。 第二金属层设置在对应于第一金属层的第一绝缘层的位置上。 第二绝缘层设置在第二金属层和第一绝缘层上。 第三金属层设置在与第二绝缘层中的第二金属层对应的位置上。 两个相邻的第二金属层之间的距离小于两个相邻的第一金属层之间的距离。
    • 6. 发明申请
    • THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
    • 薄膜晶体管阵列基板及其制造方法
    • US20110278563A1
    • 2011-11-17
    • US12838107
    • 2010-07-16
    • SUNG-HUI HUANGWei-Chou LanTed-Hong Shinn
    • SUNG-HUI HUANGWei-Chou LanTed-Hong Shinn
    • H01L27/12H01L21/84H01L21/34H01L29/786
    • H01L27/1225
    • A thin film transistor array substrate includes a substrate, a gate layer, a gate insulating layer, a source/drain layer, a patterned protective layer, an oxide semiconductor layer, a resin layer and a pixel electrode. The gate layer is disposed on the substrate. The gate insulating layer is disposed on the gate layer and the substrate. The source/drain layer is disposed on the gate insulating layer. The patterned protective layer is disposed on the source/drain layer and exposes a portion of the source/drain layer. The oxide semiconductor layer is disposed on the patterned protective layer and electrically connected to the source/drain layer. The resin layer is disposed on the oxide semiconductor layer and covers the oxide semiconductor layer. The pixel electrode is disposed on the resin layer and connects to the source/drain layer. The present invention also provides a method for making the thin film transistor array substrate. The thin film transistor array substrate can prevent leakage current.
    • 薄膜晶体管阵列基板包括基板,栅极层,栅极绝缘层,源极/漏极层,图案化保护层,氧化物半导体层,树脂层和像素电极。 栅极层设置在基板上。 栅极绝缘层设置在栅极层和基板上。 源极/漏极层设置在栅极绝缘层上。 图案化的保护层设置在源极/漏极层上并暴露源极/漏极层的一部分。 氧化物半导体层设置在图案化的保护层上并电连接到源极/漏极层。 树脂层设置在氧化物半导体层上并覆盖氧化物半导体层。 像素电极设置在树脂层上并连接到源极/漏极层。 本发明还提供了制造薄膜晶体管阵列基板的方法。 薄膜晶体管阵列基板可以防止漏电流。
    • 9. 发明授权
    • Thin film transistor array substrate and method for manufacturing the same
    • 薄膜晶体管阵列基板及其制造方法
    • US08138548B2
    • 2012-03-20
    • US12838107
    • 2010-07-16
    • Sung-Hui HuangWei-Chou LanTed-Hong Shinn
    • Sung-Hui HuangWei-Chou LanTed-Hong Shinn
    • H01L29/786
    • H01L27/1225
    • A thin film transistor array substrate includes a substrate, a gate layer, a gate insulating layer, a source/drain layer, a patterned protective layer, an oxide semiconductor layer, a resin layer and a pixel electrode. The gate layer is disposed on the substrate. The gate insulating layer is disposed on the gate layer and the substrate. The source/drain layer is disposed on the gate insulating layer. The patterned protective layer is disposed on the source/drain layer and exposes a portion of the source/drain layer. The oxide semiconductor layer is disposed on the patterned protective layer and electrically connected to the source/drain layer. The resin layer is disposed on the oxide semiconductor layer and covers the oxide semiconductor layer. The pixel electrode is disposed on the resin layer and connects to the source/drain layer. The present invention also provides a method for making the thin film transistor array substrate. The thin film transistor array substrate can prevent leakage current.
    • 薄膜晶体管阵列基板包括基板,栅极层,栅极绝缘层,源极/漏极层,图案化保护层,氧化物半导体层,树脂层和像素电极。 栅极层设置在基板上。 栅极绝缘层设置在栅极层和基板上。 源极/漏极层设置在栅极绝缘层上。 图案化的保护层设置在源极/漏极层上并暴露源极/漏极层的一部分。 氧化物半导体层设置在图案化的保护层上并电连接到源极/漏极层。 树脂层设置在氧化物半导体层上并覆盖氧化物半导体层。 像素电极设置在树脂层上并连接到源极/漏极层。 本发明还提供了制造薄膜晶体管阵列基板的方法。 薄膜晶体管阵列基板可以防止漏电流。