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1. 发明申请

US20130217622A1 EXENDIN-4 ANALOGUE PEGYLATED WITH POLYETHYLENE GLYCOL OR DERIVATIVE THEREOF, PREPARATION METHOD THEREOF, AND PHARMACEUTICAL COMPOSTION FOR PREVENTING OR TREATING DIABETES, CONTAINING SAME AS ACTIVE INGREDIENT 审中-公开
标题翻译：用聚乙烯甘油或其衍生物聚乙二醇醚化合物的EXENDIN-4模拟物，其制备方法和用于预防或治疗糖尿病的药物组合物，其含有作为活性成分
公开(公告)号：US20130217622A1
公开(公告)日：2013-08-22
申请号：US13882361
申请日：2012-06-28
申请人： Sung Kwon Lee , Won Bae Kim , Seulki Lee , Tae Hyung Kim
发明人： Sung Kwon Lee , Won Bae Kim , Seulki Lee , Tae Hyung Kim
IPC分类号： A61K47/48
CPC分类号： A61K47/02 , A61K9/0019 , A61K9/2018 , A61K9/2059 , A61K9/4858 , A61K9/4866 , A61K38/2278 , A61K47/26 , A61K47/60 , C07K14/57563
摘要： The present disclosure relates to an exendin-4 analogue PEGylated with polyethylene glycol or a derivative thereof, a preparation method, and a pharmaceutical composition for prevention or treatment of diabetes containing the same as an active ingredient. According to the present invention, the yield of an exendin-4 analogue can be increased via the selective PEGylation by using exendin-4 in which a cysteine is introduced into #40 site of the C-terminal, and treatment effect of medications can be increased, so that the exendin-4 analogue can be usefully applied as a composition for prevention or treatment of diseases caused by insulin hypersecretion.
摘要翻译：本公开内容涉及用聚乙二醇或其衍生物聚乙二醇化的毒蜥外泌肽-4类似物，制备方法和用于预防或治疗含有其作为活性成分的糖尿病的药物组合物。根据本发明，通过使用将半胱氨酸引入C末端的＃40位点的毒蜥外泌肽-4，可以通过选择性聚乙二醇化来增加毒蜥外泌肽-4类似物的产率，并且可以增加药物的治疗效果，使得毒蜥外泌肽-4类似物可有效地用作预防或治疗由胰岛素分泌过高引起的疾病的组合物。

2. 发明授权

US09321825B2 N-terminal modified PEG-TRAIL 有权
标题翻译： N-末端修饰的PEG-TRAIL
公开(公告)号：US09321825B2
公开(公告)日：2016-04-26
申请号：US12304121
申请日：2007-06-12
申请人： Kang Choon Lee , Su Young Chae , Yu Seok Youn , Won Bae Kim , Sung Kwon Lee
发明人： Kang Choon Lee , Su Young Chae , Yu Seok Youn , Won Bae Kim , Sung Kwon Lee
IPC分类号： C07K14/52 , C07K14/525 , A61K38/19 , A61K47/48 , C07K14/705
CPC分类号： A61K47/60 , A61K38/19 , A61K38/191 , B01D15/361 , C07K14/52 , C07K14/525 , C07K14/70575 , C07K2319/73 , G01N30/96
摘要： Disclosed herein are an N-terminal modified PEG-TRAIL conjugate and a preparation method and use thereof. The PEG-TAIL conjugate has pharmaceutical activity identical or similar to that of native TRAIL (TNF-related apoptosis-inducing ligand) with extended in vivo half-life and enhanced stability. Compared to native TRAIL, the PEG-TAIL conjugate exhibits high solubility and solution stability, with highly improved pharmacokinetic profiles. Thus, the PEG-TAIL conjugate may be very useful for preventing and treating proliferative diseases and autoimmune diseases.
摘要翻译：本文公开了N-末端修饰的PEG-TRAIL缀合物及其制备方法和用途。 PEG-TAIL缀合物具有与具有延长的体内半衰期和增强的稳定性的天然TRAIL（TNF-相关凋亡诱导配体）相同或相似的药物活性。与天然TRAIL相比，PEG-TAIL缀合物显示高溶解度和溶液稳定性，具有高度改善的药代动力学特征。因此，PEG-TAIL缀合物可能非常有用于预防和治疗增殖性疾病和自身免疫性疾病。

3. 发明申请

US20090203599A1 N-TERMINAL MODIFIED PEG-TRAIL, METHOD FOR PREPARING AND USES THEREOF 有权
标题翻译： N-末端修饰的PEG-TRAIL，其制备方法和用途
公开(公告)号：US20090203599A1
公开(公告)日：2009-08-13
申请号：US12304121
申请日：2007-06-12
申请人： Kang Choon Lee , Su Young Chae , Yu Seok Youn , Won Bae Kim , Sung Kwon Lee
发明人： Kang Choon Lee , Su Young Chae , Yu Seok Youn , Won Bae Kim , Sung Kwon Lee
IPC分类号： A61K38/16 , C07K14/00 , C07K1/00
CPC分类号： A61K47/60 , A61K38/19 , A61K38/191 , B01D15/361 , C07K14/52 , C07K14/525 , C07K14/70575 , C07K2319/73 , G01N30/96
摘要： Disclosed herein are an N-terminal modified PEG-TRAIL conjugate and a preparation method and use thereof. The PEG-TAIL conjugate has pharmaceutical activity identical or similar to that of native TRAIL (TNF-related apoptosis-inducing ligand) with extended in vivo half-life and enhanced stability. Compared to native TRAIL, the PEG-TAIL conjugate exhibits high solubility and solution stability, with highly improved pharmacokinetic profiles. Thus, the PEG-TAIL conjugate may be very useful for preventing and treating proliferative diseases and autoimmune diseases.
摘要翻译：本文公开了N-末端修饰的PEG-TRAIL缀合物及其制备方法和用途。 PEG-TAIL缀合物具有与具有延长的体内半衰期和增强的稳定性的天然TRAIL（TNF-相关凋亡诱导配体）相同或相似的药物活性。与天然TRAIL相比，PEG-TAIL缀合物显示高溶解度和溶液稳定性，具有高度改善的药代动力学特征。因此，PEG-TAIL缀合物可能非常有用于预防和治疗增殖性疾病和自身免疫性疾病。

4. 发明授权

US06391764B1 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06391764B1
公开(公告)日：2002-05-21
申请号：US09705704
申请日：2000-11-06
申请人： Sung Kwon Lee
发明人： Sung Kwon Lee
IPC分类号： H01L214763
CPC分类号： H01L21/76801 , H01L21/76828
摘要： A method for fabricating a semiconductor device includes the steps of: forming a transistor on a semiconductor substrate; forming a first interlayer insulating film over the entire structure including the transistor; planarizing the first interlayer insulating film; forming a stabilized insulating film consisting of an insulating material having low thermal expansion and shrinkage on the first interlayer insulating film; forming an interconnection line on the stabilized insulating film; forming a second interlayer insulating film on the stabilized insulating film to cover the interconnection line; and forming a metal electrode on the second interlayer insulating film in order to contact the semiconductor substrate. The interconnection line on the interlayer insulating film does not move as a result of the thermal treatment process, and thus does not cause shorts with the metal electrode. As a result, the leakage current is prevented and the electrical properties of the semiconductor is improved.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成晶体管; 在包括晶体管的整个结构上形成第一层间绝缘膜; 平面化第一层间绝缘膜; 在第一层间绝缘膜上形成由热膨胀和收缩率低的绝缘材料构成的稳定绝缘膜; 在稳定绝缘膜上形成互连线; 在所述稳定绝缘膜上形成第二层间绝缘膜以覆盖所述互连线; 以及在所述第二层间绝缘膜上形成金属电极以与所述半导体衬底接触。作为热处理工艺的结果，层间绝缘膜上的互连线不会移动，因此不会引起金属电极的短路。结果，防止了漏电流，提高了半导体的电特性。

5. 发明授权

US06589828B2 Fabricating a thin film transistor having better punch through resistance and hot carrier effects 失效
标题翻译：制造具有更好的穿通电阻和热载流子效应的薄膜晶体管
公开(公告)号：US06589828B2
公开(公告)日：2003-07-08
申请号：US09737774
申请日：2000-12-18
申请人： Sung Kwon Lee
发明人： Sung Kwon Lee
IPC分类号： H01L2100
CPC分类号： H01L27/127 , H01L27/11 , H01L27/1108 , H01L27/1214 , H01L29/66765 , H01L29/78624
摘要： Fabricating thin film transistors. A gate electrode is formed on a substrate. A gate oxide film is then formed on the gate electrode. A polysilicon layer is deposited on the gate oxide film. An impurity ion is implanted into the polysilicon layer to control a threshold voltage of the polysilicon layer. A mask is formed on the polysilicon layer above the gate electrode, having the same width as the gate electrode. A second impurity ion is implanted into the exposed portion of the polysilicon layer using the mask, to form a lightly doped offset region on a drain region. The mask is removed. A second mask is formed on the polysilicon layer so as to cover a portion of the gate electrode and the light doped offset region. A Third impurity ion is implanted into the polysilicon layer using the second mask to form source/drain regions. The mask is removed.
摘要翻译：制造薄膜晶体管。在基板上形成栅电极。然后在栅电极上形成栅极氧化膜。在栅极氧化膜上沉积多晶硅层。将杂质离子注入到多晶硅层中以控制多晶硅层的阈值电压。掩模形成在栅电极上方的多晶硅层上，具有与栅电极相同的宽度。使用掩模将第二杂质离子注入到多晶硅层的暴露部分中，以在漏区上形成轻掺杂的偏移区域。去除面具。在多晶硅层上形成第二掩模，以覆盖栅极电极和掺杂光的偏移区域的一部分。使用第二掩模将第三杂质离子注入到多晶硅层中以形成源/漏区。去除面具。

6. 发明授权

US06436806B2 Semiconductor device manufacturing method for preventing electrical shorts between lower and upper interconnection layers 有权
标题翻译：用于防止下互连层和上互连层之间的电短路的半导体器件制造方法
公开(公告)号：US06436806B2
公开(公告)日：2002-08-20
申请号：US09750229
申请日：2000-12-29
申请人： Sung Kwon Lee
发明人： Sung Kwon Lee
IPC分类号： H01L214763
CPC分类号： H01L21/02129 , H01L21/02126 , H01L21/022 , H01L21/31625 , H01L21/76801 , H01L21/76819
摘要： A method for manufacturing a semiconductor device is provided which suppresses migration of lower interconnectors formed on a borophosphosilicate glass (BPSG) layer toward upper interconnectors as a result of secondary reflowing of the BPSG layer during subsequent thermal processing, thereby preventing the formation of electrical shorts. The semiconductor device manufacturing method includes: forming a transistor; depositing a first interlevel dielectric film (ILD) to cover the transistor; depositing a BPSG layer as a planarization layer on the first interlevel dielectric film; reflowing the BPSG layer; etching the BPSG layer using Ar ion sputtering until a portion of the film is exposed, thereby planarizing the surfaces of the first ILD and the BPSG layers forming an interconnector on the exposed portion of the first interlevel dielectric film; depositing a second interlevel dielectric film to cover the interconnector and the BPSG layer; and forming metal electrodes on the second interlevel dielectric film, the metal electrodes being in contact with predetermined regions of the transistor.
摘要翻译：提供一种制造半导体器件的方法，其在随后的热处理期间由于BPSG层的二次回流而抑制了形成在硼磷硅酸盐玻璃（BPSG）层上的下部互连器向上部互连器的迁移，从而防止形成电气短路。半导体器件制造方法包括：形成晶体管; 沉积第一层间绝缘膜（ILD）以覆盖晶体管; 在第一层间绝缘膜上沉积BPSG层作为平坦化层; 回流BPSG层; 使用Ar离子溅射对BPSG层进行蚀刻，直到膜的一部分露出，从而在第一层间绝缘膜的暴露部分上平坦化形成互连器的第一ILD和BPSG层的表面; 沉积第二层间绝缘膜以覆盖互连器和BPSG层; 以及在所述第二层间电介质膜上形成金属电极，所述金属电极与所述晶体管的预定区域接触。

7. 发明授权

US07956654B2 Predriver and output driver circuit using the same 失效
标题翻译：前驱和输出驱动电路使用相同
公开(公告)号：US07956654B2
公开(公告)日：2011-06-07
申请号：US12455595
申请日：2009-06-04
申请人： Sung Kwon Lee
发明人： Sung Kwon Lee
IPC分类号： H03B1/00
CPC分类号： H03K19/018521
摘要： An output driver circuit includes a predriver control signal generation unit receiving a pull-up code signal, a pull-down code signal, a predriver selection signal and a read control signal and generating a pull-up control signal and a pull-down control signal; a predriver driven in response to the pull-up control signal and the pull-down control signal and receiving an internal data to drive a pull-up driving signal and a pull-down driving signal; and a driver receiving the pull-up driving signal and the pull-down driving signal and driving an output data outputted to a DQ pad, wherein the pull-up control signal and the pull-down control signal are enabled when the predriver is selected in a read operation period and a preset combination of the code signals is inputted.
摘要翻译：输出驱动器电路包括接收上拉代码信号的预驱动控制信号生成单元，下拉代码信号，预驱动选择信号和读控制信号，并产生上拉控制信号和下拉控制信号 ; 响应于上拉控制信号和下拉控制信号驱动的预驱动器，并接收内部数据以驱动上拉驱动信号和下拉驱动信号; 以及接收上拉驱动信号和下拉驱动信号并驱动输出到DQ焊盘的输出数据的驱动器的驱动器，其中当选择预驱动器时，上拉控制信号和下拉控制信号被使能输入读取操作期间和代码信号的预设组合。

8. 发明申请

US20100194448A1 Predriver and output driver circuit using the same 失效
标题翻译：前驱和输出驱动电路使用相同
公开(公告)号：US20100194448A1
公开(公告)日：2010-08-05
申请号：US12455595
申请日：2009-06-04
申请人： Sung Kwon Lee
发明人： Sung Kwon Lee
IPC分类号： H03K3/00
CPC分类号： H03K19/018521
摘要： An output driver circuit includes a predriver control signal generation unit receiving a pull-up code signal, a pull-down code signal, a predriver selection signal and a read control signal and generating a pull-up control signal and a pull-down control signal; a predriver driven in response to the pull-up control signal and the pull-down control signal and receiving an internal data to drive a pull-up driving signal and a pull-down driving signal; and a driver receiving the pull-up driving signal and the pull-down driving signal and driving an output data outputted to a DQ pad, wherein the pull-up control signal and the pull-down control signal are enabled when the predriver is selected in a read operation period and a preset combination of the code signals is inputted.
摘要翻译：输出驱动器电路包括接收上拉代码信号的预驱动控制信号生成单元，下拉代码信号，预驱动选择信号和读控制信号，并产生上拉控制信号和下拉控制信号 ; 响应于上拉控制信号和下拉控制信号驱动的预驱动器，并接收内部数据以驱动上拉驱动信号和下拉驱动信号; 以及接收上拉驱动信号和下拉驱动信号并驱动输出到DQ焊盘的输出数据的驱动器的驱动器，其中当选择预驱动器时，上拉控制信号和下拉控制信号被使能输入读取操作期间和代码信号的预设组合。

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