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1. 发明授权

US5741739A Manufacturing method of a charge storage electrode by using cylindrical oxide patterns 失效
标题翻译：通过使用圆柱形氧化物图案的电荷存储电极的制造方法
公开(公告)号：US5741739A
公开(公告)日：1998-04-21
申请号：US723582
申请日：1996-10-01
申请人： Sung Chun Cho , Kyung Dong Yoo
发明人： Sung Chun Cho , Kyung Dong Yoo
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L28/82 , H01L28/60
摘要： The present invention disclosed a structure of a charge storage electrode the and manufacturing method therefor. The present invention features forming initial oxide pattern(s) having viscous property at certain temperatures on a barrier layer as rectangular bar-shaped pattern(s) and applying heat to the oxide pattern(s) to transform the initial oxide pattern(s) to cylindrical oxide pattern(s); depositing polysilicon layer on the cylindrical oxide pattern(s); etching each end of the portions of the polysilicon layer and removing the oxide pattern(s); so as to provide a charge storage electrode structure having at least one conduit(s) which is formed with a polysilicon. The charge storage electrode structure according to the present invention has an increased effective surface area and is manufactured by a relatively simple method facilitating the manufacture of highly integrated semiconductor device.
摘要翻译：本发明公开了电荷存储电极的结构及其制造方法。本发明的特征在于，在阻挡层上的特定温度下具有粘性的初始氧化物图形作为矩形棒状图案，并向氧化物图案施加热量以将初始氧化物图案转化为圆柱形氧化物图案; 在圆柱形氧化物图案上沉积多晶硅层; 蚀刻多晶硅层的各部分的每一端并去除氧化物图案; 以提供具有形成有多晶硅的至少一个导管的电荷存储电极结构。根据本发明的电荷存储电极结构具有增加的有效表面积，并且通过有利于制造高度集成的半导体器件的相对简单的方法来制造。

2. 发明授权

US06660590B2 Vertical transistor and method of manufacturing thereof 有权
标题翻译：垂直晶体管及其制造方法
公开(公告)号：US06660590B2
公开(公告)日：2003-12-09
申请号：US10329570
申请日：2002-12-27
申请人： Kyung Dong Yoo
发明人： Kyung Dong Yoo
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L29/7827
摘要： The present invention discloses a vertical transistor wherein source/drain regions are formed by using a self-alignment method without using a latest photolithography, channels are formed via a selective epitaxial growth (hereinafter, referred to as ‘SEG’) method and gate oxide films are formed at the both ends of channels to be more efficient than devices having the same channel length, and a method of manufacturing thereof, the vertical transistor comprising: a source region formed on a semiconductor substrate; a drain region formed substantially above the source region; a vertical channel, one end of the channel being contact to the source region and the other end being contact to the drain region; and a gate electrode, formed on the substrate, surrounding the sides of the channel and the drain region, said gate electrode electrically isolated with the source region by a nitride pattern disposed therebetween, isolated with the drain region by a nitride spacer formed on the sidewalls of the drain region and isolated with channel by a gate oxide film covering the sidewalls of the channel and the exposed under surface of the drain region.
摘要翻译：本发明公开了一种垂直晶体管，其中源极/漏极区域通过使用自对准方法而不使用最新的光刻法形成，通过选择性外延生长形成通道（以下称为“SEG”）法和栅极氧化膜形成在通道的两端以比具有相同沟道长度的器件更有效率及其制造方法，该垂直晶体管包括：形成在半导体衬底上的源极区; 形成在所述源极区域基本上方的漏极区域; 一个垂直通道，一个通道的一端与源区接触，而另一端与漏区接触; 以及栅极电极，形成在所述基板上，围绕所述沟道和所述漏极区域的侧面，所述栅极电极与所述源极区域隔着氮化物图案，所述氮化物图案与所述栅极电极隔离，所述氮化物图案通过在所述侧壁上形成的氮化物间隔物与所述漏极区隔离的漏极区域并且通过覆盖沟道的侧壁和漏极区域的暴露的下表面的栅极氧化物膜与沟道隔离。

3. 发明授权

US07138324B2 Method of inhibiting degradation of gate oxide film 有权
标题翻译：抑制栅极氧化膜退化的方法
公开(公告)号：US07138324B2
公开(公告)日：2006-11-21
申请号：US11293124
申请日：2005-12-05
申请人： Kyung Dong Yoo
发明人： Kyung Dong Yoo
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/02321 , H01L21/02252 , H01L21/02304 , H01L21/28247 , H01L21/31155 , H01L21/76801 , H01L21/76825 , H01L21/76829
摘要： A method of inhibiting degradation of a transistor gate oxide film by high density plasma is disclosed. After a gate electrode is formed, impurity is implanted on the surface of an oxide film, thereby changing surface characteristics of the oxide film to scatter ultraviolet rays which are factors of degradation of the gate insulating film. Accordingly, the ultraviolet rays are prevented from being permeated into a gate insulating oxide film.
摘要翻译：公开了一种通过高密度等离子体抑制晶体管栅极氧化膜的劣化的方法。在形成栅电极之后，在氧化膜的表面上注入杂质，从而改变氧化膜的表面特性，以散射作为栅绝缘膜劣化因素的紫外线。因此，防止紫外线渗透到栅绝缘氧化膜中。

4. 发明授权

US06878990B2 Vertical transistor and method of manufacturing thereof 有权
标题翻译：垂直晶体管及其制造方法
公开(公告)号：US06878990B2
公开(公告)日：2005-04-12
申请号：US10703637
申请日：2003-11-10
申请人： Kyung Dong Yoo
发明人： Kyung Dong Yoo
IPC分类号： H01L21/336 , H01L29/78 , H01L29/76
CPC分类号： H01L29/66666 , H01L29/7827
摘要： The present invention discloses a vertical transistor wherein source/drain regions are formed by using a self-alignment method without using a latest photolithography, channels are formed via a selective epitaxial growth (hereinafter, referred to as ‘SEG’) method and gate oxide films are formed at the both ends of channels to be more efficient than devices having the same channel length, and a method of manufacturing thereof, the vertical transistor comprising: a source region formed on a semiconductor substrate; a drain region formed substantially above the source region; a vertical channel, one end of the channel being contact to the source region and the other end being contact to the drain region; and a gate electrode, formed on the substrate, surrounding the sides of the channel and the drain region, said gate electrode electrically isolated with the source region by a nitride pattern disposed therebetween, isolated with the drain region by a nitride spacer formed on the sidewalls of the drain region and isolated with channel by a gate oxide film covering the sidewalls of the channel and the exposed under surface of the drain region.
摘要翻译：本发明公开了一种垂直晶体管，其中源极/漏极区域通过使用自对准方法而不使用最新的光刻法形成，通过选择性外延生长形成通道（以下称为“SEG”）法和栅极氧化膜形成在通道的两端以比具有相同沟道长度的器件更有效率及其制造方法，该垂直晶体管包括：形成在半导体衬底上的源极区; 形成在所述源极区域基本上方的漏极区域; 一个垂直通道，一个通道的一端与源区接触，而另一端与漏区接触; 以及栅极电极，形成在所述衬底上，围绕所述沟道和所述漏极区域的侧面，所述栅极电极与所述源极区域间隔着氮化物图案，所述氮化物图案与所述栅极电极隔离，所述氮化物图案与所述漏极区隔开，的漏极区域并且通过覆盖沟道的侧壁和漏极区域的暴露的下表面的栅极氧化物膜与沟道隔离。

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