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1. 发明申请

US20060289999A1 Selective copper alloy interconnections in semiconductor devices and methods of forming the same 审中-公开
标题翻译：半导体器件中的选择性铜合金互连及其形成方法
公开(公告)号：US20060289999A1
公开(公告)日：2006-12-28
申请号：US11389868
申请日：2006-03-27
申请人： Hyo-Jong Lee , Sun-Jung Lee , Bong-Seok Suh , Hong-Jae Shin , Nae-In Lee , Kyoung-Woo Lee , Se-Young Jeong , Jeong-Hoon Ahn , Soo-Geun Lee
发明人： Hyo-Jong Lee , Sun-Jung Lee , Bong-Seok Suh , Hong-Jae Shin , Nae-In Lee , Kyoung-Woo Lee , Se-Young Jeong , Jeong-Hoon Ahn , Soo-Geun Lee
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L21/76807 , H01L21/76846 , H01L21/76847 , H01L21/76864 , H01L21/76871 , H01L21/76877 , H01L21/76883 , H01L23/53233 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A selective copper alloy interconnection in a semiconductor device is provided. The interconnection includes a substrate, a dielectric formed on the substrate, and a first interconnection formed in the dielectric. The first interconnection has a first pure copper pattern. In addition, a second interconnection having a larger width than the first interconnection is formed in the dielectric. The second interconnection has a copper alloy pattern. The copper alloy pattern may be an alloy layer formed of copper (Cu) and an additive material. A method of forming the selective copper alloy pattern is also provided.
摘要翻译：提供半导体器件中的选择性铜合金互连。互连包括衬底，形成在衬底上的电介质和形成在电介质中的第一互连。第一个互连具有第一个纯铜图案。此外，在电介质中形成具有大于第一互连的宽度的第二互连。第二互连具有铜合金图案。铜合金图案可以是由铜（Cu）和添加剂材料形成的合金层。还提供了形成选择性铜合金图案的方法。

2. 发明授权

US08228069B2 Test apparatus for determining if adjacent contacts are short-circuited and semiconductor integrated circuit devices that include such test apparatus 有权
标题翻译：用于确定相邻触点是否短路的测试装置和包括这种测试装置的半导体集成电路器件
公开(公告)号：US08228069B2
公开(公告)日：2012-07-24
申请号：US12344024
申请日：2008-12-24
申请人： Sun-Jung Lee , Hong-Jae Shin
发明人： Sun-Jung Lee , Hong-Jae Shin
IPC分类号： G01R31/08
CPC分类号： G01R31/31717 , G11C11/41 , G11C29/02 , G11C29/025 , G11C29/50008
摘要： A test apparatus includes a plurality of pairs of test contacts on a semiconductor substrate; a first test structure which includes a plurality of first test interconnection layers and a first body interconnection layer that is electrically connected to the first test interconnection layers, each of the first test interconnection layers being electrically connected to at least one test contact; and a second test structure which includes a plurality of second test interconnection layers and a second body interconnection layer that is electrically connected to the second test interconnection layers, each of the second test interconnection layers being electrically connected to at least one test contact.
摘要翻译：测试装置包括在半导体衬底上的多对测试触点; 第一测试结构，其包括多个第一测试互连层和电连接到第一测试互连层的第一体互连层，每个第一测试互连层电连接到至少一个测试接触; 以及第二测试结构，其包括多个第二测试互连层和电连接到第二测试互连层的第二体互连层，每个第二测试互连层电连接到至少一个测试接触。

3. 发明申请

US20090167319A1 TEST APPARATUS FOR DETERMINING IF ADJACENT CONTACTS ARE SHORT-CIRCUITED AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES THAT INCLUDE SUCH TEST APPARATUS 有权
标题翻译：用于确定相邻联系人的短路电路的测试装置和包含这种测试装置的半导体集成电路设备
公开(公告)号：US20090167319A1
公开(公告)日：2009-07-02
申请号：US12344024
申请日：2008-12-24
申请人： Sun-Jung Lee , Hong-Jae Shin
发明人： Sun-Jung Lee , Hong-Jae Shin
IPC分类号： G01R31/28
CPC分类号： G01R31/31717 , G11C11/41 , G11C29/02 , G11C29/025 , G11C29/50008
摘要： A test apparatus includes a plurality of pairs of test contacts on a semiconductor substrate; a first test structure which includes a plurality of first test interconnection layers and a first body interconnection layer that is electrically connected to the first test interconnection layers, each of the first test interconnection layers being electrically connected to at least one test contact; and a second test structure which includes a plurality of second test interconnection layers and a second body interconnection layer that is electrically connected to the second test interconnection layers, each of the second test interconnection layers being electrically connected to at least one test contact.
摘要翻译：测试装置包括在半导体衬底上的多对测试触点; 第一测试结构，其包括多个第一测试互连层和电连接到第一测试互连层的第一体互连层，每个第一测试互连层电连接到至少一个测试接触; 以及第二测试结构，其包括多个第二测试互连层和电连接到第二测试互连层的第二体互连层，每个第二测试互连层电连接到至少一个测试接触。

4. 发明授权

US08217393B2 Test device, SRAM test device, semiconductor integrated circuit device and methods of fabricating the same 有权
标题翻译：测试装置，SRAM测试装置，半导体集成电路装置及其制造方法
公开(公告)号：US08217393B2
公开(公告)日：2012-07-10
申请号：US12222476
申请日：2008-08-11
申请人： Sun-Jung Lee , Hong-Jae Shin
发明人： Sun-Jung Lee , Hong-Jae Shin
IPC分类号： H01L23/58 , G01R31/26
CPC分类号： G11C29/56 , G01R31/2884 , G11C11/41 , G11C29/24 , G11C29/50008 , H01L22/34 , H01L27/105 , H01L27/11 , H01L27/1108 , H01L27/1116 , H01L2924/0002 , H01L2924/00
摘要： A test device, SRAM test device, semiconductor integrated circuit, and methods of fabricating the same are provided. The test device may include a first test active region extending in one direction on a semiconductor substrate, a second test active, apart from the first test active region, extending in one direction on a semiconductor substrate, a plurality of test gate lines crossing the test active regions, a plurality of test contacts on at least one of the test active regions and test gate lines, a plurality of conducting regions electrically connecting the test contacts, and a plurality of conductive wiring lines interconnecting the plurality of test contacts, wherein an open contact chain, which electrically connects the plurality of test contacts, is formed.
摘要翻译：提供了测试装置，SRAM测试装置，半导体集成电路及其制造方法。测试装置可以包括在半导体衬底上在一个方向上延伸的第一测试有源区域，除了第一测试有源区域之外的第二测试有源区域，在半导体衬底上沿一个方向延伸，多个测试栅极线穿过测试活性区域，至少一个测试有源区域和测试栅极线路上的多个测试触点，电连接测试触点的多个导电区域和互连多个测试触点的多个导电布线，其中开放形成电连接多个测试触点的接触链。

5. 发明申请

US20090050886A1 Test device, SRAM test device, semiconductor integrated circuit device and methods of fabricating the same 有权
标题翻译：测试装置，SRAM测试装置，半导体集成电路装置及其制造方法
公开(公告)号：US20090050886A1
公开(公告)日：2009-02-26
申请号：US12222476
申请日：2008-08-11
申请人： Sun-Jung Lee , Hong-Jae Shin
发明人： Sun-Jung Lee , Hong-Jae Shin
IPC分类号： H01L23/58 , G01R31/26
CPC分类号： G11C29/56 , G01R31/2884 , G11C11/41 , G11C29/24 , G11C29/50008 , H01L22/34 , H01L27/105 , H01L27/11 , H01L27/1108 , H01L27/1116 , H01L2924/0002 , H01L2924/00
摘要： A test device, SRAM test device, semiconductor integrated circuit, and methods of fabricating the same are provided. The test device may include a first test active region extending in one direction on a semiconductor substrate, a second test active, apart from the first test active region, extending in one direction on a semiconductor substrate, a plurality of test gate lines crossing the test active regions, a plurality of test contacts on at least one of the test active regions and test gate lines, a plurality of conducting regions electrically connecting the test contacts, and a plurality of conductive wiring lines interconnecting the plurality of test contacts, wherein an open contact chain, which electrically connects the plurality of test contacts, is formed.
摘要翻译：提供了测试装置，SRAM测试装置，半导体集成电路及其制造方法。测试装置可以包括在半导体衬底上在一个方向上延伸的第一测试有源区域，除了第一测试有源区域之外的第二测试有源区域，在半导体衬底上沿一个方向延伸，多个测试栅极线穿过测试活性区域，至少一个测试有源区域和测试栅极线路上的多个测试触点，电连接测试触点的多个导电区域和互连多个测试触点的多个导电布线，其中开放形成电连接多个测试触点的接触链。

6. 发明授权

US08339349B2 Gate driving unit for liquid crystal display device and method of repairing the same 有权
标题翻译：用于液晶显示装置的门驱动单元及其修复方法
公开(公告)号：US08339349B2
公开(公告)日：2012-12-25
申请号：US12318272
申请日：2008-12-23
申请人： Hong-Jae Shin , Jeom-Jae Kim , Mike (J. S.) Lee
发明人： Hong-Jae Shin , Jeom-Jae Kim , Mike (J. S.) Lee
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G2320/0223 , G09G2330/08
摘要： A gate driving unit for a liquid crystal display device including a plurality of liquid crystal pixels, first to Nth gate lines, a plurality of liquid crystal capacitors and a plurality of thin film transistors, includes first and second clock signal lines for providing first and second clock signals; first to Nth shift registers respectively corresponding to the first to Nth gate lines, the first to Nth shift registers receiving one of the first clock signal and the second clock signal and outputting first to Nth scanning signals, respectively; a redundant repair shift register as (N+1)th shift register receiving one of first and second clock signals and outputting a repair scanning signal; a plurality of first switches for respectively connecting one of the first and second clock signal lines to the first to Nth shift registers and the redundant repair shift register; a plurality of second switches for respectively switching a connection of the first to Nth shift registers with the first to Nth gate lines; and a plurality of third switches for respectively switching a connection of the second to Nth shift registers and the redundant repair shift register with the first to Nth gate lines, wherein N is positive integer.
摘要翻译：一种用于液晶显示装置的栅极驱动单元，包括多个液晶像素，第一至第N栅极线，多个液晶电容器和多个薄膜晶体管，包括第一和第二时钟信号线，用于提供第一和第二时钟信号; 分别对应于第一至第N栅极线的第一至第N移位寄存器，第一至第N移位寄存器分别接收第一时钟信号和第二时钟信号之一并分别输出第一至第N扫描信号; 作为第（N + 1）移位寄存器的冗余修复移位寄存器，接收第一和第二时钟信号之一并输出修复扫描信号; 多个第一开关，用于分别将第一和第二时钟信号线中的一个连接到第一至第N移位寄存器和冗余修复移位寄存器; 多个第二开关，用于分别切换第一至第N移位寄存器与第一至第N栅极线的连接; 以及多个第三开关，用于分别用第一至第N栅极线切换第二至第N移位寄存器和冗余修复移位寄存器的连接，其中N为正整数。

7. 发明授权

US07989335B2 Methods of forming insulation layer patterns and methods of manufacturing semiconductor devices including insulation layer patterns 有权
标题翻译：形成绝缘层图案的方法和制造包括绝缘层图案的半导体器件的方法
公开(公告)号：US07989335B2
公开(公告)日：2011-08-02
申请号：US12661885
申请日：2010-03-25
申请人： Kyoung-Woo Lee , Hong-Jae Shin
发明人： Kyoung-Woo Lee , Hong-Jae Shin
IPC分类号： H01L21/44
CPC分类号： H01L27/10852 , H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L28/91
摘要： In a method of forming an insulation layer pattern, an insulation layer is formed on a substrate. An organic layer and a hard mask layer are successively formed on the insulation layer. A preliminary hard mask pattern having first openings is formed by patterning the hard mask layer. A hard mask pattern having the first openings and second openings is formed by patterning the preliminary hard mask pattern. Width control spacers are formed on sidewalls of the first and the second openings. An etching mask pattern is formed by etching the organic layer using the hard mask pattern as an etching mask. The insulation layer pattern having third openings is formed by etching the insulation layer using the etching mask pattern as an etching mask.
摘要翻译：在形成绝缘层图案的方法中，在基板上形成绝缘层。在绝缘层上依次形成有机层和硬掩模层。通过图案化硬掩模层形成具有第一开口的初步硬掩模图案。具有第一开口和第二开口的硬掩模图案通过图案化初步硬掩模图案而形成。宽度控制间隔件形成在第一和第二开口的侧壁上。通过使用硬掩模图案作为蚀刻掩模蚀刻有机层来形成蚀刻掩模图案。通过使用蚀刻掩模图案作为蚀刻掩模蚀刻绝缘层来形成具有第三开口的绝缘层图案。

8. 发明授权

US07855126B2 Methods of fabricating a semiconductor device using a cyclic selective epitaxial growth technique and semiconductor devices formed using the same 有权
标题翻译：使用循环选择性外延生长技术制造半导体器件的方法和使用其形成的半导体器件
公开(公告)号：US07855126B2
公开(公告)日：2010-12-21
申请号：US12043587
申请日：2008-03-06
申请人： Dong-Suk Shin , Hong-Jae Shin
发明人： Dong-Suk Shin , Hong-Jae Shin
IPC分类号： H01L21/76
CPC分类号： H01L29/66636 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/7834 , H01L29/7848
摘要： Devices and methods of fabricating a conductive pattern of such devices comprise a non-single crystalline semiconductor pattern formed on a single crystalline semiconductor substrate, an insulating spacer formed on a sidewall of the non-single crystalline semiconductor pattern, the non-single crystalline semiconductor pattern selectively recessed using a cyclic selective epitaxial growth (SEG) process, and a silicide layer formed on the recessed non-single crystalline semiconductor pattern.
摘要翻译：制造这种器件的导电图案的器件和方法包括形成在单晶半导体衬底上的非单晶半导体图案，形成在非单晶半导体图案的侧壁上的绝缘间隔物，非单晶半导体图案使用循环选择性外延生长（SEG）工艺选择性地凹陷，以及形成在凹陷的非单晶半导体图案上的硅化物层。

9. 发明申请

US20100248436A1 Methods of forming insulation layer patterns and methods of manufacturing semiconductor devices including insulation layer patterns 有权
标题翻译：形成绝缘层图案的方法和制造包括绝缘层图案的半导体器件的方法
公开(公告)号：US20100248436A1
公开(公告)日：2010-09-30
申请号：US12661885
申请日：2010-03-25
申请人： Kyoung-Woo Lee , Hong-Jae Shin
发明人： Kyoung-Woo Lee , Hong-Jae Shin
IPC分类号： H01L21/336 , G03F7/20
CPC分类号： H01L27/10852 , H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L28/91
摘要： In a method of forming an insulation layer pattern, an insulation layer is formed on a substrate. An organic layer and a hard mask layer are successively formed on the insulation layer. A preliminary hard mask pattern having first openings is formed by patterning the hard mask layer. A hard mask pattern having the first openings and second openings is formed by patterning the preliminary hard mask pattern. Width control spacers are formed on sidewalls of the first and the second openings. An etching mask pattern is formed by etching the organic layer using the hard mask pattern as an etching mask. The insulation layer pattern having third openings is formed by etching the insulation layer using the etching mask pattern as an etching mask.
摘要翻译：在形成绝缘层图案的方法中，在基板上形成绝缘层。在绝缘层上依次形成有机层和硬掩模层。通过图案化硬掩模层形成具有第一开口的初步硬掩模图案。具有第一开口和第二开口的硬掩模图案通过图案化初步硬掩模图案而形成。宽度控制间隔件形成在第一和第二开口的侧壁上。通过使用硬掩模图案作为蚀刻掩模蚀刻有机层来形成蚀刻掩模图案。通过使用蚀刻掩模图案作为蚀刻掩模蚀刻绝缘层来形成具有第三开口的绝缘层图案。

10. 发明授权

US07595253B2 Method of forming the semiconductor device 失效
标题翻译：形成半导体器件的方法
公开(公告)号：US07595253B2
公开(公告)日：2009-09-29
申请号：US11797827
申请日：2007-05-08
申请人： II-Young Yoon , Hong-Jae Shin , Nae-In Lee , Jae-Ouk Choo , Ja-Eung Koo
发明人： II-Young Yoon , Hong-Jae Shin , Nae-In Lee , Jae-Ouk Choo , Ja-Eung Koo
IPC分类号： H01L21/76
CPC分类号： H01L21/31053 , H01L21/76229
摘要： Example embodiments provide a semiconductor device and a method of forming the same. According to the method, a capping insulation pattern may be formed to cover the top surface of a filling insulation pattern in a trench. The capping insulation pattern may have an etch selectivity according to the filling insulation pattern. As a result, the likelihood that the filling insulation layer may be etched by various cleaning processes and the process removing the buffer insulation pattern may be reduced or prevented.
摘要翻译：示例性实施例提供半导体器件及其形成方法。根据该方法，可以形成覆盖绝缘图案以覆盖沟槽中的填充绝缘图案的顶表面。封盖绝缘图案可以根据填充绝缘图案具有蚀刻选择性。结果，可以减少或防止填充绝缘层可以通过各种清洁处理蚀刻的可能性以及去除缓冲绝缘图案的过程。

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