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1. 发明授权

US07420872B2 Command decoder circuit of semiconductor memory device 有权
标题翻译：半导体存储器件的指令译码电路
公开(公告)号：US07420872B2
公开(公告)日：2008-09-02
申请号：US11647761
申请日：2006-12-29
申请人： Sun Suk Yang , Jung Hoon Park
发明人： Sun Suk Yang , Jung Hoon Park
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C7/222 , G11C11/4096
摘要： A command decoder circuit generates command signals for performing internal operations and according to external command signals, according to values of the write latency values and whether write latency is an even numbered or odd-numbered value.
摘要翻译：命令解码器电路根据写等待时间值的值和写等待时间是否为偶数或奇数值，产生用于执行内部操作和外部命令信号的命令信号。

2. 发明授权

US06906968B2 Input buffer of semiconductor memory device 有权
标题翻译：半导体存储器件的输入缓冲器
公开(公告)号：US06906968B2
公开(公告)日：2005-06-14
申请号：US10737962
申请日：2003-12-18
申请人： Kwang Hyun Kim , Sun Suk Yang
发明人： Kwang Hyun Kim , Sun Suk Yang
IPC分类号： G11C7/06 , G11C7/10 , G11C29/12 , G11C7/00
CPC分类号： G11C29/12015 , G11C7/06 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/109 , G11C7/1093 , G11C11/401 , G11C29/12 , G11C29/1201
摘要： An input buffer of a semiconductor memory device includes a first buffer block for buffering an input data through a delay path selected from a plurality of delay paths, and a second buffer block for buffering an input data strobe signal through a delay path selected from a plurality of delay paths, wherein the plurality of delay paths of the first buffer block and the plurality of delay paths of the second buffer block are identically formed by the same devices, and the corresponding delay paths are selected from the plurality of delay paths according to the same selecting signals. Although the input buffer fails to obtain a margin of a data setup and hold time in an input/output sense amplifier due to variations of the data setup and hold time by maximum and minimum values of tDQSS in a write operation mode, the input buffer can easily obtain the margin of the data setup and hold time in response to a special test mode signal.
摘要翻译：半导体存储器件的输入缓冲器包括用于通过从多个延迟路径中选择的延迟路径来缓冲输入数据的第一缓冲器块和用于通过从多个延迟路径中选择的延迟路径来缓冲输入数据选通信号的第二缓冲器块的延迟路径，其中第一缓冲块的多个延迟路径和第二缓冲块的多个延迟路径由相同的设备相同地形成，并且根据相应的设备从多个延迟路径中选择相应的延迟路径相同的选择信号。虽然输入缓冲器由于数据设置和保持时间的变化而在输入/输出读出放大器中无法获得数据建立和保持时间的余量，但是在写入操作模式中tDQSS的最大值和最小值，输入缓冲器可以响应于特殊的测试模式信号容易获得数据建立和保持时间的余量。

3. 发明授权

US07613069B2 Address latch circuit of semiconductor memory device 有权
标题翻译：半导体存储器件的地址锁存电路
公开(公告)号：US07613069B2
公开(公告)日：2009-11-03
申请号：US11683532
申请日：2007-03-08
申请人： Sun Suk Yang
发明人： Sun Suk Yang
IPC分类号： G11C8/06
CPC分类号： G11C8/06 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C2207/107
摘要： An address latch circuit of a semiconductor memory device is provided. The address latch circuit includes a first address latch part, which latches a first address signal fed from outside according to a first address latch signal and outputs a second address signal. An address shift part shifts the second address signal according to a divided clock, which is divided from an external clock, and a write latency signal, and outputs a third address signal. A second address latch part latches the third address signal according to a second address latch signal and outputs a fourth address signal.
摘要翻译：提供半导体存储器件的地址锁存电路。地址锁存电路包括第一地址锁存部分，其根据第一地址锁存信号锁存从外部馈送的第一地址信号，并输出第二地址信号。地址移位部分根据从外部时钟划分的分频时钟和写等待时间信号来移位第二地址信号，并输出第三地址信号。第二地址锁存部分根据第二地址锁存信号锁存第三地址信号，并输出第四地址信号。

4. 发明授权

US07304528B2 Charge pump with speed control 有权
标题翻译：充电泵带速度控制
公开(公告)号：US07304528B2
公开(公告)日：2007-12-04
申请号：US11533023
申请日：2006-09-19
申请人： Kwang Hyun Kim , Sun Suk Yang
发明人： Kwang Hyun Kim , Sun Suk Yang
IPC分类号： H03K3/01
CPC分类号： G11C5/145 , H03K3/0315
摘要： A charge pump circuit includes a test mode control unit for generating a plurality of control signals according to a test mode enable signal and an input signal and fixing one of the plurality of the control signals depending upon whether a fuse has been cut or not, a ring oscillator for outputting an output frequency of which varies according to an output of the test mode control unit, and a charge pump for generating a high voltage, which is higher than an external voltage, according to an output of the ring oscillator.
摘要翻译：电荷泵电路包括测试模式控制单元，用于根据测试模式使能信号和输入信号产生多个控制信号，并且根据是否已经切断熔丝来固定多个控制信号中的一个; 输出其输出频率根据测试模式控制单元的输出而变化的环形振荡器，以及根据环形振荡器的输出产生高于外部电压的高电压的电荷泵。

5. 发明授权

US07061826B2 Command decoder of semiconductor memory device 有权
标题翻译：半导体存储器件的命令解码器
公开(公告)号：US07061826B2
公开(公告)日：2006-06-13
申请号：US10908549
申请日：2005-05-16
申请人： Sun Suk Yang
发明人： Sun Suk Yang
IPC分类号： G11C8/00
CPC分类号： G11C7/109 , G11C7/1072 , G11C7/1078 , G11C7/1093 , G11C8/18
摘要： A command decoder is provided for controlling internal circuits of a semiconductor chip to operate in synchronism with a first internal clock signal having a pulse width, which is twice as wide as that of an external clock signal, and a second internal clock signal having an opposite phase to the first internal clock signal. An internal operation controller controls internal circuits of a semiconductor chip to operate in synchronism with a first internal clock signal having a pulse width, which is N times as wide as that of an external clock signal, if the command signal is received at a first rising edge of the external clock signal, and controls the internal circuits of the semiconductor chip to operate in synchronism with a second internal clock signal having an opposite phase to the first internal clock signal, if the command signal is received at a second rising edge of the external clock signal.
摘要翻译：提供了一种命令解码器，用于控制半导体芯片的内部电路与具有与外部时钟信号的两倍宽的脉冲宽度的第一内部时钟信号同步操作，以及具有相反的第二内部时钟信号相到第一个内部时钟信号。内部操作控制器控制半导体芯片的内部电路与第一内部时钟信号同步操作，该第一内部时钟信号的脉冲宽度是外部时钟信号的N倍，如果在第一次上升时接收到命令信号并且如果在第二内部时钟信号的第二上升沿接收到指令信号，则控制半导体芯片的内部电路与与第一内部时钟信号具有相反相位的第二内部时钟信号同步地操作外部时钟信号。

6. 发明授权

US08902682B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08902682B2
公开(公告)日：2014-12-02
申请号：US13615371
申请日：2012-09-13
申请人： Sun Suk Yang
发明人： Sun Suk Yang
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C29/06
摘要： A semiconductor memory device includes an internal signal generation block configured to generate a control signal which is enabled from a generation time of an internal active signal enabled if it is determined that a combination of external commands in synchronization with a rising edge of an external clock inputted from an outside is a preset combination, to a disable time an internal idle signal; and an internal command signal generation block configured to generate an internal write signal if it is determined that a combination of counting signals counted during an enable period of the control signal is a first combination and generate an internal precharge signal if it is determined that the combination of the counting signals is a second combination.
摘要翻译：半导体存储器件包括内部信号产生模块，其被配置为：如果确定与输入的外部时钟的上升沿同步的外部命令的组合，则产生可从内部有效信号的生成时间使能的控制信号从外部是预设组合，禁用时间内部空闲信号; 以及内部命令信号生成块，其被配置为如果确定在所述控制信号的使能周期期间计数的计数信号的组合是第一组合并且如果确定所述组合则生成内部预充电信号，则生成内部写入信号的计数信号是第二组合。

7. 发明申请

US20070291573A1 Semiconductor integrated circuit having data input/output circuit and method for inputting data using the same 有权
标题翻译：具有数据输入/输出电路的半导体集成电路及使用其的数据输入方法
公开(公告)号：US20070291573A1
公开(公告)日：2007-12-20
申请号：US11647490
申请日：2006-12-29
申请人： Sun Suk Yang
发明人： Sun Suk Yang
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G11C7/1078 , G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/1087 , G11C7/109 , G11C8/12
摘要： An apparatus includes a control unit for generating an input control signal to select a global input/output line to which data is transmitted. A repeater receives data from the global input/output line to output the data to a global input/output line corresponding to the input control signal. A plurality of input drivers receive the data from the repeater to transmit the data to a local input/output line connected to each memory bank.
摘要翻译：一种装置包括：控制单元，用于产生输入控制信号以选择发送数据的全局输入/输出线。中继器从全局输入/输出线接收数据，将数据输出到与输入控制信号对应的全局输入/输出线。多个输入驱动器从中继器接收数据以将数据发送到连接到每个存储体的本地输入/输出线。

8. 发明授权

US06320457B1 High level voltage generator 有权
标题翻译：高电平电压发生器
公开(公告)号：US06320457B1
公开(公告)日：2001-11-20
申请号：US09603050
申请日：2000-06-26
申请人： Sun Suk Yang
发明人： Sun Suk Yang
IPC分类号： G05F110
CPC分类号： H02M3/073
摘要： A high level voltage generator, comprising: high voltage level detection means for comparing a potential level of a high voltage node and a target level to generate a first pumping enable control signal; first oscillation means for periodically generating a first pulse signal by the first pumping enable control signal from the high voltage level detection means; first high voltage pump means for pumping the potential level of the high voltage node by the first pulse signal from the first oscillation means; pumping drivability control means for detecting a length of an active time of the first pumping enable control signal to generate a second pumping enable control signal; second oscillation means for generating a second pulse signal by the second pumping enable control signal from the pumping drivablity control means; and second high voltage pump means for pumping the potential level of the high voltage node by the second pulse signal from the second oscillation means.
摘要翻译：一种高电平电压发生器，包括：高电压电平检测装置，用于比较高电压节点的电位电平和目标电平，以产生第一泵送使能控制信号; 第一振荡装置，用于通过来自高电压电平检测装置的第一泵浦使能控制信号周期性地产生第一脉冲信号; 第一高压泵装置，用于通过来自第一振荡装置的第一脉冲信号来泵送高压节点的电位电平; 抽吸驾驶员控制装置，用于检测第一泵送使能控制信号的有效时间的长度以产生第二泵送使能控制信号; 第二振荡装置，用于通过来自泵送驱动力控制装置的第二泵浦使能控制信号产生第二脉冲信号; 以及第二高压泵装置，用于通过来自第二振荡装置的第二脉冲信号来泵送高压节点的电位电平。

9. 发明授权

US08422323B2 Multi-bit test circuit of semiconductor memory apparatus 失效
标题翻译：半导体存储器件的多位测试电路
公开(公告)号：US08422323B2
公开(公告)日：2013-04-16
申请号：US12966650
申请日：2010-12-13
申请人： Sun Suk Yang
发明人： Sun Suk Yang
IPC分类号： G11C29/00 , G11C7/00 , G11C8/00
CPC分类号： G11C29/28
摘要： A multi-bit test circuit for a semiconductor memory is configured to cause an active command to activate active signals. At least two active signals are respectively inputted to a plurality of banks at different timings in a multi-bit test mode.
摘要翻译：用于半导体存储器的多位测试电路被配置为使得有效命令激活有效信号。在多位测试模式中，以不同的定时将至少两个有效信号分别输入到多个存储体。

10. 发明授权

US08199606B2 Semiconductor memory apparatus and method of controlling the same 有权
标题翻译：半导体存储装置及其控制方法
公开(公告)号：US08199606B2
公开(公告)日：2012-06-12
申请号：US12650412
申请日：2009-12-30
申请人： Sun Suk Yang
发明人： Sun Suk Yang
IPC分类号： G11C8/00
CPC分类号： G11C8/06
摘要： A semiconductor memory apparatus includes: an address buffer configured to buffer an input address and generate a buffered address; a command buffer configured to buffer a chip selection command and generate a buffered command; a latch control unit configured to receive an internal clock and the buffered command and generate a latch control signal; and an address latch unit configured to latch the buffered address based on the latch control signal.
摘要翻译：半导体存储装置包括：地址缓冲器，被配置为缓冲输入地址并生成缓冲地址; 配置为缓冲芯片选择命令并生成缓冲命令的命令缓冲器; 闩锁控制单元，被配置为接收内部时钟和缓冲命令并产生锁存控制信号; 以及地址锁存单元，被配置为基于所述锁存控制信号来锁存缓冲的地址。

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