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1. 发明授权

US08106914B2 Fused multiply-add functional unit 有权
标题翻译：熔融多重功能单元
公开(公告)号：US08106914B2
公开(公告)日：2012-01-31
申请号：US11952858
申请日：2007-12-07
申请人： Stuart Oberman , Ming Y. Siu , David C. Tannenbaum
发明人： Stuart Oberman , Ming Y. Siu , David C. Tannenbaum
IPC分类号： G06T1/20 , G06T1/00 , G06T15/00 , G06F15/16 , G06F7/38
CPC分类号： G06F9/30014 , G06F9/30112 , G06F9/3012 , G06F9/30123 , G06F9/3851 , G06F9/3887 , G06F9/3893 , G06T1/20
摘要： A functional unit is added to a graphics processor to provide direct support for double-precision arithmetic, in addition to the single-precision functional units used for rendering. The double-precision functional unit can execute a number of different operations, including fused multiply-add, on double-precision inputs using data paths and/or logic circuits that are at least double-precision width. The double-precision and single-precision functional units can be controlled by a shared instruction issue circuit, and the number of copies of the double-precision functional unit included in a core can be less than the number of copies of the single-precision functional units, thereby reducing the effect of adding support for double-precision on chip area.
摘要翻译：除了用于渲染的单精度功能单元之外，功能单元被添加到图形处理器以提供对双精度算术的直接支持。双精度功能单元可以使用至少双精度宽度的数据路径和/或逻辑电路在双精度输入上执行多种不同的操作，包括融合乘法运算。双精度和单精度功能单元可以由共享指令发出电路控制，核心中包含的双精度功能单元的份数可以小于单精度功能的副本数单位，从而降低了对双精度芯片面积的支持的影响。

2. 发明申请

US20090150654A1 FUSED MULTIPLY-ADD FUNCTIONAL UNIT 有权
标题翻译：加热多功能功能单元
公开(公告)号：US20090150654A1
公开(公告)日：2009-06-11
申请号：US11952858
申请日：2007-12-07
申请人： Stuart Oberman , Ming Y. Siu , David C. Tannenbaum
发明人： Stuart Oberman , Ming Y. Siu , David C. Tannenbaum
IPC分类号： G06F9/302
CPC分类号： G06F9/30014 , G06F9/30112 , G06F9/3012 , G06F9/30123 , G06F9/3851 , G06F9/3887 , G06F9/3893 , G06T1/20
摘要： A functional unit is added to a graphics processor to provide direct support for double-precision arithmetic, in addition to the single-precision functional units used for rendering. The double-precision functional unit can execute a number of different operations, including fused multiply-add, on double-precision inputs using data paths and/or logic circuits that are at least double-precision width. The double-precision and single-precision functional units can be controlled by a shared instruction issue circuit, and the number of copies of the double-precision functional unit included in a core can be less than the number of copies of the single-precision functional units, thereby reducing the effect of adding support for double-precision on chip area.
摘要翻译：除了用于渲染的单精度功能单元之外，功能单元被添加到图形处理器以提供对双精度算术的直接支持。双精度功能单元可以使用至少双精度宽度的数据路径和/或逻辑电路在双精度输入上执行多种不同的操作，包括融合乘法运算。双精度和单精度功能单元可以由共享指令发出电路控制，核心中包含的双精度功能单元的份数可以小于单精度功能的副本数单位，从而降低了对双精度芯片面积的支持的影响。

3. 发明授权

US08051123B1 Multipurpose functional unit with double-precision and filtering operations 有权
标题翻译：多用途功能单元具有双精度和过滤操作
公开(公告)号：US08051123B1
公开(公告)日：2011-11-01
申请号：US11611800
申请日：2006-12-15
申请人： Stuart Oberman , Ming Y. Siu
发明人： Stuart Oberman , Ming Y. Siu
IPC分类号： G06F7/38
CPC分类号： G06F7/38 , G06F7/483 , G06F7/5443 , G06F7/57
摘要： A multipurpose arithmetic functional unit selectively performs planar attribute interpolation, unary function approximation, double-precision arithmetic, and/or arbitrary filtering functions such as texture filtering, bilinear filtering, or anisotropic filtering by iterating through a multi-step multiplication operation with partial products (partial results) accumulated in an accumulation register. Shared multiplier and adder circuits are advantageously used to implement the product and sum operations for unary function approximation and planar interpolation; the same multipliers and adders are also leveraged to implement double-precision multiplication and addition.
摘要翻译：多用途算术功能单元通过迭代通过部分乘积的多步乘法运算来选择性地执行平面属性插值，一元函数近似，双精度算术和/或任意滤波函数，例如纹理滤波，双线性滤波或各向异性滤波，部分结果）积累在累积寄存器中。共享乘法器和加法器电路有利地用于实现一元函数近似和平面内插的乘积和求和运算; 同样的乘法器和加法器也被用来实现双精度乘法和加法。

4. 发明授权

US08860737B2 Programmable graphics processor for multithreaded execution of programs 有权
标题翻译：用于多线程执行程序的可编程图形处理器
公开(公告)号：US08860737B2
公开(公告)日：2014-10-14
申请号：US11458633
申请日：2006-07-19
申请人： John Erik Lindholm , Brett W. Coon , Stuart F. Oberman , Ming Y. Siu , Matthew P. Gerlach
发明人： John Erik Lindholm , Brett W. Coon , Stuart F. Oberman , Ming Y. Siu , Matthew P. Gerlach
IPC分类号： G06F15/16 , G06F15/80 , G06T1/20 , G06T15/00 , G06F12/08 , G06T15/10
CPC分类号： G06T15/005 , G06F12/0811 , G06F12/0815 , G06F12/0875 , G06T15/10
摘要： A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.
摘要翻译：处理单元包括多个执行流水线，每个执行流水线连接到第一输入部分，用于接收用于像素处理的输入数据和用于接收用于顶点处理的输入数据的第二输入部分和用于存储经处理的像素数据的第一输出部分和用于存储经处理的顶点数据的第二输出部分。经处理的顶点数据被光栅化并扫描转换为用作像素处理的输入数据的像素数据。经处理的像素数据被输出到光栅分析器。

5. 发明授权

US08539204B2 Cooperative thread array reduction and scan operations 有权
标题翻译：合作线程数组减少和扫描操作
公开(公告)号：US08539204B2
公开(公告)日：2013-09-17
申请号：US12890227
申请日：2010-09-24
申请人： Brian Fahs , Ming Y. Siu , Brett W. Coon , John R. Nickolls , Lars Nyland
发明人： Brian Fahs , Ming Y. Siu , Brett W. Coon , John R. Nickolls , Lars Nyland
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/522 , G06F8/458 , G06F9/3004 , G06F9/30087 , G06F9/30145 , G06F9/3851
摘要： One embodiment of the present invention sets forth a technique for performing aggregation operations across multiple threads that execute independently. Aggregation is specified as part of a barrier synchronization or barrier arrival instruction, where in addition to performing the barrier synchronization or arrival, the instruction aggregates (using reduction or scan operations) values supplied by each thread. When a thread executes the barrier aggregation instruction the thread contributes to a scan or reduction result, and waits to execute any more instructions until after all of the threads have executed the barrier aggregation instruction. A reduction result is communicated to each thread after all of the threads have executed the barrier aggregation instruction and a scan result is communicated to each thread as the barrier aggregation instruction is executed by the thread.
摘要翻译：本发明的一个实施例提出了一种用于跨独立执行的多个线程执行聚合操作的技术。聚合被指定为屏障同步或屏障到达指令的一部分，其中除了执行屏障同步或到达之外，指令聚合（使用缩减或扫描操作）由每个线程提供的值。当线程执行屏障聚合指令时，线程有助于扫描或缩小结果，并等待执行任何更多指令，直到所有线程都执行了阻挡聚合指令为止。在所有线程执行了屏障聚合指令之后，向每个线程传送减少结果，并且当线程执行屏障聚合指令时，将扫描结果传送给每个线程。

6. 发明授权

US08522000B2 Trap handler architecture for a parallel processing unit 有权
标题翻译：并行处理单元的陷阱处理器架构
公开(公告)号：US08522000B2
公开(公告)日：2013-08-27
申请号：US12569831
申请日：2009-09-29
申请人： Michael C. Shebanow , Jack Choquette , Brett W. Coon , Steven J. Heinrich , Aravind Kalaiah , John R. Nickolls , Daniel Salinas , Ming Y. Siu , Tommy Thorn , Nicholas Wang
发明人： Michael C. Shebanow , Jack Choquette , Brett W. Coon , Steven J. Heinrich , Aravind Kalaiah , John R. Nickolls , Daniel Salinas , Ming Y. Siu , Tommy Thorn , Nicholas Wang
IPC分类号： G06F9/00
CPC分类号： G06F9/327 , G06F9/3851 , G06F9/3861
摘要： A trap handler architecture is incorporated into a parallel processing subsystem such as a GPU. The trap handler architecture minimizes design complexity and verification efforts for concurrently executing threads by imposing a property that all thread groups associated with a streaming multi-processor are either all executing within their respective code segments or are all executing within the trap handler code segment.
摘要翻译：陷阱处理器架构被并入到诸如GPU的并行处理子系统中。陷阱处理器架构通过强加与流式多处理器相关联的所有线程组都在其各自的代码段内执行或全部在陷阱处理程序代码段内执行的属性来最小化并发执行线程的设计复杂性和验证工作。

7. 发明申请

US20110078427A1 TRAP HANDLER ARCHITECTURE FOR A PARALLEL PROCESSING UNIT 有权
标题翻译：并行处理单元的TRAP操作架构
公开(公告)号：US20110078427A1
公开(公告)日：2011-03-31
申请号：US12569831
申请日：2009-09-29
申请人： Michael C. Shebanow , Jack Choquette , Brett W. Coon , Steven J. Heinrich , Aravind Kalaiah , John R. Nickolls , Daniel Salinas , Ming Y. Siu , Tommy Thorn , Nicholas Wang
发明人： Michael C. Shebanow , Jack Choquette , Brett W. Coon , Steven J. Heinrich , Aravind Kalaiah , John R. Nickolls , Daniel Salinas , Ming Y. Siu , Tommy Thorn , Nicholas Wang
IPC分类号： G06F9/38
CPC分类号： G06F9/327 , G06F9/3851 , G06F9/3861
摘要： A trap handler architecture is incorporated into a parallel processing subsystem such as a GPU. The trap handler architecture minimizes design complexity and verification efforts for concurrently executing threads by imposing a property that all thread groups associated with a streaming multi-processor are either all executing within their respective code segments or are all executing within the trap handler code segment.
摘要翻译：陷阱处理器架构被并入到诸如GPU的并行处理子系统中。陷阱处理器架构通过强加与流式多处理器相关联的所有线程组都在其各自的代码段内执行或全部在陷阱处理程序代码段内执行的属性来最小化并发执行线程的设计复杂性和验证工作。

8. 发明授权

US09195460B1 Using condition codes in the presence of non-numeric values 有权
标题翻译：在非数值存在的情况下使用条件代码
公开(公告)号：US09195460B1
公开(公告)日：2015-11-24
申请号：US11415781
申请日：2006-05-02
申请人： Robert Steven Glanville , John Erik Lindholm , Ming Y. Siu
发明人： Robert Steven Glanville , John Erik Lindholm , Ming Y. Siu
IPC分类号： G06F9/45 , G06F9/30
CPC分类号： G06F9/30094 , G06F9/30058
摘要： Systems and methods for compiling programs using condition codes and executing those programs when non-numeric values are present allow for explicit handling of non-numeric values. In addition to the conventional condition code values of positive, negative, and zero, a fourth value may be encoded, not a number (NaN) representing a non-numeric value. New condition tests are defined that explicitly account for condition code values of NaN. A compiler may produce code using the new condition tests to represent if and if-else statements. The code including the new condition tests generates deterministic results during execution when non-numeric values are present.
摘要翻译：使用条件代码编译程序的系统和方法，并且当存在非数字值时执行这些程序允许显式处理非数字值。除了正，负和零的常规条件代码值之外，第四值可以被编码，而不是表示非数值的数字（NaN）。定义新条件测试，明确说明NaN的条件代码值。编译器可以使用新的条件测试来生成代码来表示if和if-else语句。包含新条件测试的代码在执行时产生确定性结果，当非数值存在时。

9. 发明授权

US09058672B2 Using a pixel offset for evaluating a plane equation 有权
标题翻译：使用像素偏移来评估平面方程
公开(公告)号：US09058672B2
公开(公告)日：2015-06-16
申请号：US12898537
申请日：2010-10-05
申请人： John Erik Lindholm , Henry Packard Moreton , Ming Y. Siu , Stuart F. Oberman
发明人： John Erik Lindholm , Henry Packard Moreton , Ming Y. Siu , Stuart F. Oberman
IPC分类号： G06K9/32 , G06T3/40
CPC分类号： G06T3/4007
摘要： One embodiment of the present invention sets forth a technique controlling the pixel location at which the plane equation is evaluated. Multiple pixel offsets (dx, dy) may be specified that each define to a sub-pixel sample position. Attributes are then calculated for each sub-pixel sample position that is covered by a geometric primitive. One advantage of the technique is that anti-aliasing quality may be improved since high frequency color components may be selectively supersampled for particular geometric primitives.
摘要翻译：本发明的一个实施例提出了一种控制平面方程被评估的像素位置的技术。可以指定多个像素偏移（dx，dy），每个像素偏移定义为子像素采样位置。然后对由几何图元覆盖的每个子像素样本位置计算属性。该技术的一个优点是可以改善抗混叠质量，因为可以对特定几何基元选择性地超采样高频彩色分量。

10. 发明授权

US08645638B2 Shared single-access memory with management of multiple parallel requests 有权
标题翻译：具有管理多个并行请求的共享单访问存储器
公开(公告)号：US08645638B2
公开(公告)日：2014-02-04
申请号：US13466057
申请日：2012-05-07
申请人： Brett W. Coon , Ming Y. Siu , Weizhong Xu , Stuart F. Oberman , John R. Nickolls , Peter C. Mills
发明人： Brett W. Coon , Ming Y. Siu , Weizhong Xu , Stuart F. Oberman , John R. Nickolls , Peter C. Mills
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/084 , Y02D10/13
摘要： A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.
摘要翻译：多线程处理器中的并发线程使用内存。任何可寻址的存储位置都可以由任何并发线程访问，但一次只能访问一个位置。存储器耦合到并行处理引擎，其产生一组并行存储器访问请求，每个指定对于不同请求可能相同或不同的目标地址。序列化逻辑选择一个目标地址，并确定哪个请求指定所选择的目标地址。允许所有这些请求并行进行，而其他请求被推迟。可以通过序列化逻辑重新生成和处理延迟请求，以便通过一次访问组中的每个不同的目标地址来满足一组请求。

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