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1. 发明授权

US08898408B2 Memory controller-independent memory mirroring 有权
标题翻译：内存控制器独立内存镜像
公开(公告)号：US08898408B2
公开(公告)日：2014-11-25
申请号：US13323428
申请日：2011-12-12
申请人： Stuart Allen Berke , William Sauber
发明人： Stuart Allen Berke , William Sauber
IPC分类号： G06F13/00
CPC分类号： G06F11/1048 , G06F11/1658 , G06F11/1666 , G06F11/167
摘要： A method of memory controller-independent memory mirroring includes providing a mirroring association between a first memory segment and a second memory segment that is independent of a memory controller. A memory buffer receives data from the memory controller that is directed to a first memory location in the first memory segment. The memory buffer writes the data, independent of the memory controller, to both the first memory segment and the second memory segment according to the mirroring association. The memory buffer receives a plurality of read commands from the memory controller that are directed to the first memory location in the first memory segment and, in response, reads data from an alternating one of the first memory segment and the second memory segment and stores both first data from the first memory segment and second data from the second memory segment.
摘要翻译：一种与存储器控制器无关的内存镜像的方法包括提供独立于存储器控制器的第一存储器段和第二存储器段之间的镜像关联。存储器缓冲器从存储器控制器接收指向第一存储器段中的第一存储器位置的数据。存储器缓冲器根据镜像关联将数据独立于存储器控制器写入第一存储器段和第二存储器段。存储器缓冲器从存储器控制器接收指向第一存储器段中的第一存储器位置的多个读取命令，并且作为响应，从第一存储器段和第二存储器段中的交替的一个读取数据并且存储两个来自第一存储器段的第一数据和来自第二存储器段的第二数据。

2. 发明申请

US20130254474A1 SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION OF MEMORY 审中-公开
标题翻译：用于减少存储器功耗的系统和方法
公开(公告)号：US20130254474A1
公开(公告)日：2013-09-26
申请号：US13893739
申请日：2013-05-14
申请人： Stuart Allen Berke , William Sauber
发明人： Stuart Allen Berke , William Sauber
IPC分类号： G06F1/32
CPC分类号： G06F1/3275 , G06F1/3203 , Y02D10/14
摘要： Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. A method for reducing power consumption in memory may include tracking, by an operating system executing on a processor, one or more logical units of a memory system that are in use. The method may also include setting, by the operating system, a variable indicating a portion of the memory system in use based on the logical units of the memory system in use. The method may additionally include refreshing one or more of the one or more logical units of the memory system based on the variable.
摘要翻译：公开了用于减少与存储器件中的功耗有关的问题和缺点的系统和方法。用于降低存储器中的功耗的方法可以包括通过在处理器上执行的操作系统跟踪正在使用的存储器系统的一个或多个逻辑单元。该方法还可以包括由操作系统基于正在使用的存储器系统的逻辑单元来设置指示正在使用的存储器系统的一部分的变量。该方法可以另外包括基于该变量刷新存储器系统的一个或多个逻辑单元中的一个或多个。

3. 发明申请

US20130151767A1 MEMORY CONTROLLER-INDEPENDENT MEMORY MIRRORING 有权
标题翻译：内存控制器独立存储器镜像
公开(公告)号：US20130151767A1
公开(公告)日：2013-06-13
申请号：US13323428
申请日：2011-12-12
申请人： Stuart Allen Berke , William Sauber
发明人： Stuart Allen Berke , William Sauber
IPC分类号： G06F12/16
CPC分类号： G06F11/1048 , G06F11/1658 , G06F11/1666 , G06F11/167
摘要： A method of memory controller-independent memory mirroring includes providing a mirroring association between a first memory segment and a second memory segment that is independent of a memory controller. A memory buffer receives data from the memory controller that is directed to a first memory location in the first memory segment. The memory buffer writes the data, independent of the memory controller, to both the first memory segment and the second memory segment according to the mirroring association. The memory buffer receives a plurality of read commands from the memory controller that are directed to the first memory location in the first memory segment and, in response, reads data from an alternating one of the first memory segment and the second memory segment and stores both first data from the first memory segment and second data from the second memory segment.
摘要翻译：一种与存储器控制器无关的内存镜像的方法包括提供独立于存储器控制器的第一存储器段和第二存储器段之间的镜像关联。存储器缓冲器从存储器控制器接收指向第一存储器段中的第一存储器位置的数据。存储器缓冲器根据镜像关联将数据独立于存储器控制器写入第一存储器段和第二存储器段。存储器缓冲器从存储器控制器接收指向第一存储器段中的第一存储器位置的多个读取命令，并且作为响应，从第一存储器段和第二存储器段中的交替的一个读取数据并且存储两个来自第一存储器段的第一数据和来自第二存储器段的第二数据。

4. 发明申请

US20130054949A1 MEMORY COMPATIBILITY SYSTEM AND METHOD 有权
标题翻译：记忆兼容系统和方法
公开(公告)号：US20130054949A1
公开(公告)日：2013-02-28
申请号：US13222938
申请日：2011-08-31
申请人： Stuart Allen Berke , William Sauber
发明人： Stuart Allen Berke , William Sauber
IPC分类号： G06F15/177
CPC分类号： G06F9/44557 , G06F11/1016 , G06F13/409 , G11C5/04 , G11C5/14 , Y02D10/14 , Y02D10/151
摘要： An apparatus including a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard, a second socket configured to accept a memory module therein, the second socket and the memory module conforming to a second standard, a memory buffer module communicatively coupled to the first connector and the second socket, the memory buffer module configured to receive signals associated with the first standard from the first connector and output signals associated with the second standard to the second socket, and a virtualization module communicatively coupled to the memory buffer module, the first connector, and the second socket, the virtualization module configured to receive first initialization data associated with the second standard from the second socket and output second initialization data associated with the first standard to the processing system.
摘要翻译：一种装置，包括被配置为装配到处理系统中的第一插座中的第一连接器，所述第一连接器和第一插座符合第一标准，第二插座被配置为接纳其中的存储器模块，所述第二插座和所述存储器模块符合第二标准，通信地耦合到第一连接器和第二插座的存储缓冲器模块，所述存储器缓冲模块被配置为从所述第一连接器接收与所述第一标准相关联的信号，并将与所述第二标准相关联的信号输出到所述第二插座，以及虚拟化模块，其通信地耦合到所述存储器缓冲器模块，所述第一连接器和所述第二插座，所述虚拟化模块被配置为从所述第二插座接收与所述第二标准相关联的第一初始化数据，并将与所述第一标准相关联的第二初始化数据输出到处理系统。

5. 发明授权

US08639918B2 Memory compatibility system and method 有权
标题翻译：内存兼容系统和方法
公开(公告)号：US08639918B2
公开(公告)日：2014-01-28
申请号：US13222938
申请日：2011-08-31
申请人： Stuart Allen Berke , William Sauber
发明人： Stuart Allen Berke , William Sauber
IPC分类号： G06F15/177 , G06F3/00 , G06F13/12
CPC分类号： G06F9/44557 , G06F11/1016 , G06F13/409 , G11C5/04 , G11C5/14 , Y02D10/14 , Y02D10/151
摘要： An apparatus including a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard, a second socket configured to accept a memory module therein, the second socket and the memory module conforming to a second standard, a memory buffer module communicatively coupled to the first connector and the second socket, the memory buffer module configured to receive signals associated with the first standard from the first connector and output signals associated with the second standard to the second socket, and a virtualization module communicatively coupled to the memory buffer module, the first connector, and the second socket, the virtualization module configured to receive first initialization data associated with the second standard from the second socket and output second initialization data associated with the first standard to the processing system.
摘要翻译：一种装置，包括被配置为装配到处理系统中的第一插座中的第一连接器，所述第一连接器和第一插座符合第一标准，第二插座被配置为接纳其中的存储器模块，所述第二插座和所述存储器模块符合第二标准，通信地耦合到第一连接器和第二插座的存储缓冲器模块，所述存储器缓冲模块被配置为从所述第一连接器接收与所述第一标准相关联的信号，并将与所述第二标准相关联的信号输出到所述第二插座，以及虚拟化模块，其通信地耦合到所述存储器缓冲器模块，所述第一连接器和所述第二插座，所述虚拟化模块被配置为从所述第二插座接收与所述第二标准相关联的第一初始化数据，并将与所述第一标准相关联的第二初始化数据输出到处理系统。

6. 发明申请

US20130254506A1 MEMORY CONTROLLER-INDEPENDENT MEMORY SPARING 有权
标题翻译：内存控制器独立存储器空间
公开(公告)号：US20130254506A1
公开(公告)日：2013-09-26
申请号：US13426296
申请日：2012-03-21
申请人： Stuart Allen Berke , William Sauber
发明人： Stuart Allen Berke , William Sauber
IPC分类号： G06F12/02
CPC分类号： G06F11/1666 , G06F11/1658 , G06F11/20
摘要： An information handling system (IHS) includes a memory controller, a memory device, and firmware. A failing memory region and a spare memory region are included on the memory device. A memory buffer in the memory device is coupled to the failing memory region and the spare memory region. The memory buffer is operable to perform copy operations without instruction from the memory controller in order to copy data from the failing memory region to the spare memory region in response to firmware operations performed by the firmware. Firmware operations may include instructing the memory controller to produce additional refresh or calibration operation time periods, or providing an instruction to perform a data transfer operation to the spare memory region. The memory buffer is also operable to route requests from the memory controller to one of the failing memory region and the spare memory region during the copy operations.
摘要翻译：信息处理系统（IHS）包括存储器控制器，存储器件和固件。存储器件中包括故障存储器区域和备用存储器区域。存储器件中的存储器缓冲器耦合到故障存储器区域和备用存储器区域。存储器缓冲器可操作以执行没有来自存储器控制器的指令的复制操作，以便响应于由固件执行的固件操作将数据从故障存储器区域复制到备用存储器区域。固件操作可以包括指示存储器控制器产生额外的刷新或校准操作时间段，或提供执行到备用存储器区域的数据传送操作的指令。存储器缓冲器还可操作以在复制操作期间将来自存储器控制器的请求路由到故障存储器区域和备用存储器区域之一。

7. 发明授权

US08468295B2 System and method for reducing power consumption of memory 有权
标题翻译：降低内存功耗的系统和方法
公开(公告)号：US08468295B2
公开(公告)日：2013-06-18
申请号：US12629681
申请日：2009-12-02
申请人： Stuart Allen Berke , William Sauber
发明人： Stuart Allen Berke , William Sauber
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G11C7/00 , H03M13/00
CPC分类号： G06F1/3275 , G06F1/3203 , Y02D10/14
摘要： Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. A method for reducing power consumption in memory may include tracking, by an operating system executing on a processor, one or more logical units of a memory system that are in use. The method may also include setting, by the operating system, a variable indicating a portion of the memory system in use based on the logical units of the memory system in use. The method may additionally include refreshing one or more of the one or more logical units of the memory system based on the variable.
摘要翻译：公开了用于减少与存储器件中的功耗有关的问题和缺点的系统和方法。用于降低存储器中的功耗的方法可以包括通过在处理器上执行的操作系统跟踪正在使用的存储器系统的一个或多个逻辑单元。该方法还可以包括由操作系统基于正在使用的存储器系统的逻辑单元来设置指示正在使用的存储器系统的一部分的变量。该方法可以另外包括基于该变量刷新存储器系统的一个或多个逻辑单元中的一个或多个。

8. 发明申请

US20130111308A1 SYSTEM AND METHOD FOR SELECTIVE ERROR CHECKING 有权
标题翻译：用于选择性错误检查的系统和方法
公开(公告)号：US20130111308A1
公开(公告)日：2013-05-02
申请号：US13283051
申请日：2011-10-27
申请人： William Sauber , Ayedin Nikazm , Stuart Allen Berke
发明人： William Sauber , Ayedin Nikazm , Stuart Allen Berke
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： H03M13/095 , G06F11/1004 , G06F21/53 , G06F21/64 , H03M13/09
摘要： A method of selectively enabling error checking in an information handling system, including receiving information indicating that data associated with a first memory portion in a system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory, receiving a memory access request directed to one of the first and second memory portions, transmitting data between the memory controller and the system memory in response to the memory access request, and selectively performing an error checking technique on the transmitted data based on the information.
摘要翻译：一种选择性地启用信息处理系统中的错误检查的方法，包括接收指示与系统存储器中的第一存储器部分相关联的数据的信息应该在存储器控制器和系统存储器之间的传输期间进行错误检查，并指示数据相关联系统存储器中的第二存储器部分在存储器控制器和系统存储器之间的传输期间应该没有错误检查，接收指向第一和第二存储器部分之一的存储器访问请求，在存储器控制器和存储器控制器之间传送数据响应于存储器访问请求的系统存储器，并且基于该信息选择性地对发送的数据执行错误检查技术。

9. 发明申请

US20110296098A1 System and Method for Reducing Power Consumption of Memory 审中-公开
标题翻译：降低内存功耗的系统和方法
公开(公告)号：US20110296098A1
公开(公告)日：2011-12-01
申请号：US12791563
申请日：2010-06-01
申请人： William Sauber , Stuart Allen Berke
发明人： William Sauber , Stuart Allen Berke
IPC分类号： G06F12/00
CPC分类号： G06F3/0625 , G06F1/3225 , G06F1/3275 , G06F3/0634 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G11C11/40611 , G11C11/40615 , G11C11/40618 , G11C11/40622 , Y02D10/14
摘要： Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. In accordance with one embodiment of the present disclosure, a method for improving performance and reducing power consumption in memory may include tracking whether individual units of a memory system are active or inactive. The method may also include placing inactive individual units of the memory system in a self-refresh mode, such that the inactive individual units self-refresh their contents. The method may further include placing active individual units of the memory system in a command-based refresh mode, such that the active individual units are refreshed in response to a received command to refresh their contents.
摘要翻译：公开了用于减少与存储器件中的功耗有关的问题和缺点的系统和方法。根据本公开的一个实施例，用于改善存储器的性能和降低功耗的方法可以包括跟踪存储器系统的各个单元是活动还是不活动。该方法还可以包括将存储器系统的非活动单元单元置于自刷新模式中，使得非活动单元单元自刷新其内容。该方法还可以包括将存储器系统的活动单独单元置于基于命令的刷新模式中，使得响应于接收到的刷新其内容的命令刷新活动的单个单元。

10. 发明授权

US08719493B2 Memory controller-independent memory sparing 有权
标题翻译：内存控制器独立内存备用
公开(公告)号：US08719493B2
公开(公告)日：2014-05-06
申请号：US13426296
申请日：2012-03-21
申请人： Stuart Allen Berke , William Sauber
发明人： Stuart Allen Berke , William Sauber
IPC分类号： G06F12/04
CPC分类号： G06F11/1666 , G06F11/1658 , G06F11/20
摘要： An information handling system (IHS) includes a memory controller, a memory device, and firmware. A failing memory region and a spare memory region are included on the memory device. A memory buffer in the memory device is coupled to the failing memory region and the spare memory region. The memory buffer is operable to perform copy operations without instruction from the memory controller in order to copy data from the failing memory region to the spare memory region in response to firmware operations performed by the firmware. Firmware operations may include instructing the memory controller to produce additional refresh or calibration operation time periods, or providing an instruction to perform a data transfer operation to the spare memory region. The memory buffer is also operable to route requests from the memory controller to one of the failing memory region and the spare memory region during the copy operations.
摘要翻译：信息处理系统（IHS）包括存储器控制器，存储器件和固件。存储器件中包括故障存储器区域和备用存储器区域。存储器件中的存储器缓冲器耦合到故障存储器区域和备用存储器区域。存储器缓冲器可操作以执行没有来自存储器控制器的指令的复制操作，以便响应于由固件执行的固件操作将数据从故障存储器区域复制到备用存储器区域。固件操作可以包括指示存储器控制器产生额外的刷新或校准操作时间段，或提供执行到备用存储器区域的数据传送操作的指令。存储器缓冲器还可操作以在复制操作期间将来自存储器控制器的请求路由到故障存储器区域和备用存储器区域之一。

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