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1. 发明授权

US06771105B2 Voltage controlled oscillator programmable delay cells 有权
标题翻译：压控振荡器可编程延时单元
公开(公告)号：US06771105B2
公开(公告)日：2004-08-03
申请号：US10099707
申请日：2002-03-13
申请人： Stjepan William Andrasic , Rakesh H. Patel , Chong H. Lee
发明人： Stjepan William Andrasic , Rakesh H. Patel , Chong H. Lee
IPC分类号： H03H1126
CPC分类号： H03K5/133 , H03K3/0322 , H03K3/354 , H03L7/0995 , H03L7/10
摘要： A delay cell has selectable numbers of parallel load resistance transistors operable in parallel, and a similarly selectable number of bias current transistors connectable in parallel. The delay cell is preferably differential in construction and operation. A voltage controlled oscillator (“VCO”) includes a plurality of such delay cells connected in a closed loop series. Phase locked loop (“PLL”) circuitry includes such a VCO controlled by phase/frequency detector circuitry. The PLL can have a very wide range of operating frequencies as a result of the ability to control the number of load resistance transistors and bias current transistors that are active or inactive in each delay cell. Such activation/deactivation may be programmable or otherwise controlled.
摘要翻译：延迟单元具有可并行操作的并联负载电阻晶体管的可选数量，以及可并联连接的类似可选数量的偏置电流晶体管。延迟单元优选在构造和操作上是不同的。压控振荡器（“VCO”）包括以闭环系列连接的多个这样的延迟单元。锁相环（“PLL”）电路包括由相位/频率检测器电路控制的这种VCO。由于能够控制在每个延迟单元中有效或无效的负载电阻晶体管和偏置电流晶体管的数量，PLL可以具有非常宽的工作频率范围。这种激活/去激活可以是可编程的或以其他方式控制的。

2. 发明申请

US20110211621A1 HETEROGENEOUS TRANSCEIVER ARCHITECTURE FOR WIDE RANGE PROGRAMMABILITY OF PROGRAMMABLE LOGIC DEVICES 有权
标题翻译：用于可编程逻辑器件的宽范围可编程性的异构收发器架构
公开(公告)号：US20110211621A1
公开(公告)日：2011-09-01
申请号：US13103132
申请日：2011-05-09
申请人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
发明人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
IPC分类号： H04L5/14 , H04L27/00
CPC分类号： H04L5/14 , H03K19/17744 , H04L27/00
摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
摘要翻译：可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道达到第二个相对较高的最大数据速率。相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

3. 发明授权

US08787352B2 Heterogeneous transceiver architecture for wide range programmability of programmable logic devices 有权
标题翻译：异构收发器架构，用于可编程逻辑器件的广泛可编程性
公开(公告)号：US08787352B2
公开(公告)日：2014-07-22
申请号：US13103132
申请日：2011-05-09
申请人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
发明人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
IPC分类号： H04L12/28 , H04L5/14 , H04L27/00
CPC分类号： H04L5/14 , H03K19/17744 , H04L27/00
摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
摘要翻译：可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道达到第二个相对较高的最大数据速率。相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

4. 发明授权

US07646217B2 Programmable logic device with serial interconnect 有权
标题翻译：具有串行互连的可编程逻辑器件
公开(公告)号：US07646217B2
公开(公告)日：2010-01-12
申请号：US11539006
申请日：2006-10-05
申请人： Ramanand Venkata , Rakesh H. Patel , Chong H. Lee
发明人： Ramanand Venkata , Rakesh H. Patel , Chong H. Lee
IPC分类号： H01L25/00
CPC分类号： H03K19/17736 , H03K19/17744 , H03K19/17784
摘要： In a programmable logic device, some or all of the parallel interconnect resources are replaced by serial interconnect resources within the device. Some or all of the functional blocks on the device are supplemented with serial interfaces. Although this makes the functional blocks more complex, it allows a significant reduction in the area consumed by interconnect resources. This translates into a significant reduction in device power consumption. The serial interfaces may operate synchronously from a global device clock (such as a PLL). In some cases, serial interfaces that are provided in the input/output blocks for external signalling can be omitted because the serial interfaces in the functional blocks can take over the external serial interface function as well, although in those cases the serial interfaces in the functional blocks would have to be more complex because they would have to be able to operate asynchronously with external devices.
摘要翻译：在可编程逻辑器件中，部分或全部并行互连资源由器件内的串行互连资源代替。设备上的部分或全部功能块被补充有串行接口。尽管这使得功能块更加复杂，但它允许显着减少互连资源消耗的面积。这意味着设备功耗的显着降低。串行接口可以与全局设备时钟（例如PLL）同步工作。在某些情况下，可以省略输入/输出块中提供的用于外部信号的串行接口，因为功能块中的串行接口也可以接管外部串行接口功能，尽管在这些情况下，功能中的串行接口块将不得不更复杂，因为它们必须能够与外部设备异步操作。

5. 发明申请

US20100058099A1 HETEROGENEOUS TRANSCEIVER ARCHITECTURE FOR WIDE RANGE PROGRAMMABILITY OF PROGRAMMABLE LOGIC DEVICES 有权
标题翻译：用于可编程逻辑器件的宽范围可编程性的异构收发器架构
公开(公告)号：US20100058099A1
公开(公告)日：2010-03-04
申请号：US12576507
申请日：2009-10-09
申请人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
发明人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
IPC分类号： G06F1/04 , G06F1/12
CPC分类号： H04L5/14 , H03K19/17744 , H04L27/00
摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
摘要翻译：可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道达到第二个相对较高的最大数据速率。相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

6. 发明授权

US07940814B2 Heterogeneous transceiver architecture for wide range programmability of programmable logic devices 有权
标题翻译：异构收发器架构，用于可编程逻辑器件的广泛可编程性
公开(公告)号：US07940814B2
公开(公告)日：2011-05-10
申请号：US12576507
申请日：2009-10-09
申请人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
发明人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
IPC分类号： H04J3/04
CPC分类号： H04L5/14 , H03K19/17744 , H04L27/00
摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
摘要翻译：可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道达到第二个相对较高的最大数据速率。相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

7. 发明授权

US07698482B2 Multiple data rates in integrated circuit device serial interface 有权
标题翻译：集成电路设备串行接口中的多种数据速率
公开(公告)号：US07698482B2
公开(公告)日：2010-04-13
申请号：US11177007
申请日：2005-07-08
申请人： Ramanand Venkata , Rakesh H. Patel , Chong H. Lee
发明人： Ramanand Venkata , Rakesh H. Patel , Chong H. Lee
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： H03K19/17744
摘要： A serial interface for a programmable logic device supports a wide range of data rates by providing a first number of channels supporting a first range of data rates and a second number of channels supporting a second range of data rates. The first range of data rates is preferably lower than the second range of data rates and preferably the first number of channels is higher than the second number of channels which preferably is 1. For backward compatibility with existing devices, the first number of channels in each interface preferably is four. Each channel preferably includes a physical medium attachment module and a physical coding sublayer module. Each of the higher-speed channels in the second number of channels preferably also includes a clock management unit, while the lower-speed channels in the first number of channels preferably share one or more clock management units.
摘要翻译：用于可编程逻辑器件的串行接口通过提供支持第一范围的数据速率的第一数量的通道和支持第二数据速率范围的第二数量的通道来支持宽范围的数据速率。数据速率的第一范围优选地低于数据速率的第二范围，并且优选地，第一数量的信道高于优选为1的信道的第二数量。为了与现有设备的向后兼容，每个信道中的第一数量的信道界面最好是四。每个通道优选地包括物理介质连接模块和物理编码子层模块。第二数量的频道中的每一个较高频道优选地还包括时钟管理单元，而第一数量的频道中的较低速频道优选地共享一个或多个时钟管理单元。

8. 发明授权

US08863065B1 Stacked die network-on-chip for FPGA 有权
标题翻译：用于FPGA的堆叠芯片芯片
公开(公告)号：US08863065B1
公开(公告)日：2014-10-14
申请号：US12775363
申请日：2010-05-06
申请人： Francis Man-Chit Chow , Rakesh H. Patel , Erhard Joachim Pistorius
发明人： Francis Man-Chit Chow , Rakesh H. Patel , Erhard Joachim Pistorius
IPC分类号： G06F17/50
CPC分类号： H03K19/17796 , H01L25/0657 , H01L25/18 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A programmable device system includes one or more network-on-chip (NoC) die layers vertically connected to one or more programmable chip dice layers. The NoC die layer includes interconnects, a bus or non-blocking switches, and optionally memory blocks and direct memory access engines. The NoC die layer improves on-chip communications by providing fast and direct interconnection circuitry between various parts of the programmable chip die.
摘要翻译：可编程器件系统包括垂直连接到一个或多个可编程芯片芯片层的一个或多个芯片上芯片（NoC）裸片层。 NoC模块层包括互连，总线或非阻塞开关，以及可选的存储器块和直接存储器访问引擎。 NoC裸片层通过在可编程芯片裸片的各个部分之间提供快速和直接的互连电路来改善片上通信。

9. 发明授权

US08599598B1 3T device based memory circuits and arrays 有权
标题翻译： 3T基于设备的存储器电路和阵列
公开(公告)号：US08599598B1
公开(公告)日：2013-12-03
申请号：US13287957
申请日：2011-11-02
申请人： Rakesh H. Patel , Shankar Prasad Sinha
发明人： Rakesh H. Patel , Shankar Prasad Sinha
IPC分类号： G11C11/00
CPC分类号： G11C29/00 , G11C13/0007 , G11C13/0011 , G11C13/0069 , G11C13/0097 , G11C23/00 , H01L27/11803 , H01L45/085 , H01L45/1206 , H01L45/142 , H01L45/146 , H03K19/1737
摘要： In one aspect, a memory circuit is provided. The memory circuit includes a first three-terminal (3T) resistive memory device and a second 3T resistive memory device coupled to the first 3T resistive memory device. In another aspect a memory array with memory circuits having 3T devices is provided. In yet another aspect, a method of programming a memory array is provided.
摘要翻译：一方面，提供一种存储器电路。存储器电路包括耦合到第一3T电阻存储器件的第一三端（3T）电阻存储器件和第二3T电阻存储器件。在另一方面，提供了具有3T设备的存储器电路的存储器阵列。在另一方面，提供了一种编程存储器阵列的方法。

10. 发明授权

US08000106B1 Circuit distribution to multiple integrated circuits 有权
标题翻译：电路分配到多个集成电路
公开(公告)号：US08000106B1
公开(公告)日：2011-08-16
申请号：US11969373
申请日：2008-01-04
申请人： Rakesh H. Patel
发明人： Rakesh H. Patel
IPC分类号： H05K7/00
CPC分类号： H01L23/481 , H01L24/16 , H01L25/18 , H01L2224/13099 , H01L2224/32145 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14
摘要： A semiconductor system in a package separates those circuits in a field programmable gate array (FPGA) into two substrates. In particular, the logic elements are formed in a first semiconductor substrate and certain non-logic elements are formed in a second semiconductor substrate that is in mechanical and electrical connection with the first substrate. The two substrates are enclosed in a suitable protective package and electrical connections are provided between one or both substrates and the exterior. The non-logic elements formed in the second substrate are located in circuits that would have a signal propagation delay in a conventional FPGA that is more than approximately twice the interconnect delay between the two substrates.
摘要翻译：封装中的半导体系统将现场可编程门阵列（FPGA）中的那些电路分离成两个基板。特别地，逻辑元件形成在第一半导体衬底中，并且某些非逻辑元件形成在与第一衬底机械和电连接的第二半导体衬底中。两个基板被封装在合适的保护封装中，并且在一个或两个基板和外部之间提供电连接。形成在第二基板中的非逻辑元件位于在常规FPGA中具有大于两个基板之间的互连延迟的大约两倍的信号传播延迟的电路中。

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