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1. 发明授权

US06721371B1 One sample per symbol high rate programmable parallel architecture for digital demodulation 有权
标题翻译：每个符号的一个采样高速可编程并行架构用于数字解调
公开(公告)号：US06721371B1
公开(公告)日：2004-04-13
申请号：US09477882
申请日：2000-01-05
申请人： Steven T Barham , Zachary C Bagley , Lyman D Horne
发明人： Steven T Barham , Zachary C Bagley , Lyman D Horne
IPC分类号： H04L2722
CPC分类号： H03H17/0294 , H04L25/03006
摘要： A high speed demodulator system is comprised of an analog to digital converter (ADC); a high speed demultiplexer connected to an input of the ADC; a bank of parallel programmable demodulators connected to an output of the high speed demultiplexer; a timing interface connected to the bank of parallel programmable demodulators; and a phase reference interface connected to the bank of parallel programmable demodulators and a data processor. A parallel programmable demodulator includes a reconfigurable FIR filter, has an input port for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory. The programmable FIR filter provides filtered signals to the coherent signal processor for storage in the coherent memory. The integrated circuit further includes a sequential weight processor having an input coupled to an output of the coherent memory. The sequential weight processor includes a weight memory and operates to output symbol soft decision data resulting from processing the digital input signals. The integrated circuit is programmable into one of a plurality of operating modes, including at least one of a received signal acquisition mode, a channel estimator mode, an adaptive equalizer mode, and a channel-wise differential mode.
摘要翻译：高速解调器系统由模数转换器（ADC）组成; 连接到ADC的输入的高速解复用器; 一组并行可编程解调器，连接到高速解复用器的输出端; 连接到并行可编程解调器组的定时接口; 以及连接到并行可编程解调器组的相位参考接口和数据处理器。并行可编程解调器包括可重构FIR滤波器，具有用于接收数字输入信号的输入端口和耦合到相干信号处理器和相干存储器的输出。可编程FIR滤波器将滤波信号提供给相干信号处理器，以存储在相干存储器中。集成电路还包括具有耦合到相干存储器的输出的输入的顺序权重处理器。顺序加权处理器包括权重存储器，并且操作以输出由处理数字输入信号得到的符号软判决数据。集成电路可编程为多种操作模式之一，包括接收信号采集模式，信道估计模式，自适应均衡器模式和频道方式差分模式中的至少一种。

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