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1. 发明授权

US5355362A Digital loop carrier system 失效
标题翻译：数字环路载波系统
公开(公告)号：US5355362A
公开(公告)日：1994-10-11
申请号：US966335
申请日：1992-10-26
申请人： Steven S. Gorshe , Hitoshi Sato
发明人： Steven S. Gorshe , Hitoshi Sato
IPC分类号： H04Q3/42 , H04J3/08 , H04Q11/04 , H04J3/12
CPC分类号： H04Q11/04 , H04J3/085 , H04J2203/0042 , H04J2203/0046 , H04Q2213/13103 , H04Q2213/13106 , H04Q2213/13166 , H04Q2213/13167 , H04Q2213/13174 , H04Q2213/13204 , H04Q2213/1329 , H04Q2213/13292 , H04Q2213/13299 , H04Q2213/1332 , H04Q2213/13381
摘要： A telecommunication network which includes a SONET-based digital subscriber loop carrier system that supports wideband and narrowband services. The digital subscriber loop carrier system includes a common module for performing common functions of the system and for transferring subscriber data between the system and a central office or local digital switch, and at least one service definition module, which is coupled to subscribers, for interfacing the subscribers to the system. The common module and the service definition modules are coupled by a common backplane including pulse coded modulation buses and all data, including both subscriber data and control data, are transferred per the SONET protocol. Each of the common module and service definition modules employ buses, which are also based on the SONET protocol.
摘要翻译：一种电信网络，其包括支持宽带和窄带业务的基于SONET的数字用户环路载波系统。数字用户环路载波系统包括用于执行系统的共同功能并用于在系统与中心局或本地数字交换机之间传送用户数据的公共模块以及耦合到订户的至少一个服务定义模块，用于接口系统的用户。公共模块和服务定义模块通过包括脉冲编码调制总线的公共背板耦合，并且包括用户数据和控制数据的所有数据根据SONET协议传送。公共模块和服务定义模块中的每一个采用基于SONET协议的总线。

2. 发明授权

US06529599B1 Flexible tributary unit protection method for a trunk-multiplexed metallic interface 失效
标题翻译：用于主干复用金属接口的灵活支路单元保护方法
公开(公告)号：US06529599B1
公开(公告)日：2003-03-04
申请号：US09111417
申请日：1998-07-07
申请人： Steven S. Gorshe
发明人： Steven S. Gorshe
IPC分类号： H04M900
CPC分类号： H04M1/723
摘要： In a telephone system having multiple working metallic interface units, a method and a structure provide protection by assigning to each metallic interface unit a partner unit, which is another metallic interface unit. Under this arrangement, when a failure occurs in a working metallic interface unit, its partner unit switches the ring/tip input signals of the failed metallic interface unit to a protection bus. A standby or protective unit then takes over by receiving the rerouted tip/ring signals from the protection bus. The failed working unit can then be removed from the shelf without disrupting service.
摘要翻译：在具有多个工作金属接口单元的电话系统中，方法和结构通过向每个金属接口单元分配作为另一金属接口单元的伙伴单元来提供保护。在这种布置下，当工作的金属接口单元发生故障时，其伙伴单元将故障金属接口单元的环/尖端输入信号切换到保护总线。备用或保护单元然后通过从保护总线接收重新路由的尖端/振铃信号接管。然后，故障的工作单元可以从架子上取出，而不会中断服务。

3. 发明授权

US5113187A CMI encoder circuit 失效
标题翻译： CMI编码器电路
公开(公告)号：US5113187A
公开(公告)日：1992-05-12
申请号：US673912
申请日：1991-03-25
申请人： Steven S. Gorshe
发明人： Steven S. Gorshe
IPC分类号： H03M5/06 , H03M5/12 , H03M5/14
CPC分类号： H03M5/12 , H03M5/14
摘要： A circuit having a completely synchronous and digital implementation for encoding a stream of digital data (NRZ form) into the coded marked inversion (CMI) format. The circuit includes a state machine having a predetermined number of defined legal and illegal states, an illegal state detection circuit, and an output circuit. When the state machine enters an illegal state because of, for example, the effects of noise or distortion on the digital data signal, the illegal state detection circuit forces the state machine back into a legal state.
摘要翻译：具有完全同步和数字实现的电路，用于将数字数据流（NRZ形式）编码成编码标记反转（CMI）格式。该电路包括具有预定数量的规定的合法和非法状态的状态机，非法状态检测电路和输出电路。当状态机由于例如数字数据信号的噪声或失真的影响而进入非法状态时，非法状态检测电路迫使状态机恢复到合法状态。

4. 发明授权

US4853931A Violating All Zero Octet (VAZO) detector for a zero byte time slot interchange (ZBTSI) encoder 失效
标题翻译：针对零字节时隙交换（ZBTSI）编码器违反全零字节（VAZO）检测器
公开(公告)号：US4853931A
公开(公告)日：1989-08-01
申请号：US181785
申请日：1988-04-15
申请人： Steven S. Gorshe
发明人： Steven S. Gorshe
IPC分类号： H03M5/14 , H04L25/49 , H04Q11/04
CPC分类号： H03M5/145 , H04L25/4925 , H04Q11/0435
摘要： A Violating All Zero Octet (VAZO) detector for a ZBTSI clear channel data transmission system is described, which is optimized for minimum logic gate count, minimum circuit complexity, minimum external control signals and minimum signal processing delay, in a VLSI hardware embodiment which is advantageously implemented in application specific integrated circuit (ASIC) technology. An array of logic NOR gates scans input data for zero strings of data that could combine with an all-zero octet to violate the zero string criterion enables a zero string search to be performed with a minimum of circuit complexity. The use of an input shift register to buffer input data for other portions of the associated ZBTSI encoder provides for a minimized number of gates in a VLSI implementation.
摘要翻译：描述了用于ZBTSI清除信道数据传输系统的违规全零八位字节（VAZO）检测器，其在针对最小逻辑门数，最小电路复杂度，最小外部控制信号和最小信号处理延迟的情况下进行了优化，VLSI硬件实施例是有利地在专用集成电路（ASIC）技术中实现。逻辑或非门阵列扫描可以与全零八位字节组合以消除零字符串标准的零数据串的输入数据，使得能够以最小的电路复杂度来执行零字符串搜索。使用输入移位寄存器来缓冲相关联的ZBTSI编码器的其他部分的输入数据，在VLSI实现中提供了最小数量的门。

5. 发明授权

US5878039A Bus rate adaptation and time slot assignment circuit for a sonet multiplex system 失效
标题翻译：用于Sonet多路复用系统的总线速率适配和时隙分配电路
公开(公告)号：US5878039A
公开(公告)日：1999-03-02
申请号：US637413
申请日：1996-04-24
申请人： Steven S. Gorshe , Robert W. Brooks, Jr.
发明人： Steven S. Gorshe , Robert W. Brooks, Jr.
IPC分类号： H04J3/16 , H04Q11/04 , H04J3/22
CPC分类号： H04J3/1611 , H04Q11/0478 , H04J2203/0089 , H04Q2213/1301 , H04Q2213/13204 , H04Q2213/1329 , H04Q2213/13297 , H04Q2213/13332 , H04Q2213/13393 , H04Q2213/13399
摘要： An interface device is provided which may be used to perform rate adaptation and time slot assignment, in either the transmit or receive directions, in a multiplexing unit for interfacing a high rate optical carrier line to a plurality of lower rate information carrier lines. The high rate optical carrier line may be a SONET or SDH carrier line. The interface device according to the present invention may be operationally configured to provide data rate adaptation and time slot assignment between an optical carrier line operating at an OC-12 rate with lower rate lines operating according to OC-3, OC-1, DS-3, or DS-1 protocols, or even virtual channels. A plurality of identical interface devices may be cascaded together and used to perform interface support for various channels operating at various rates, merely by manipulating the operational configuration of the individual interface devices in the cascade.
摘要翻译：提供一种接口装置，其可以用于在用于将高速率光载波线路连接到多个较低速率信息载体线路的多路复用单元中的发射或接收方向中执行速率适配和时隙分配。高速光载波线路可以是SONET或SDH载波线路。根据本发明的接口设备可以可操作地被配置为在以OC-12速率工作的光载波线路与根据OC-3，OC-1，DS-1，...之间运行的较低速率线路之间提供数据速率适配和时隙分配， 3或DS-1协议，甚至虚拟通道。多个相同的接口设备可以级联在一起，并且用于仅通过操纵级联中的各个接口设备的操作配置来对以各种速率操作的各种通道执行接口支持。

6. 发明授权

US5848065A Optimized universal card slot system for sonet multiplex equipment 失效
标题翻译：优化通用卡槽系统，用于sonet复用设备
公开(公告)号：US5848065A
公开(公告)日：1998-12-08
申请号：US584193
申请日：1996-01-11
申请人： Steven S. Gorshe , Robert W. Brooks, Jr.
发明人： Steven S. Gorshe , Robert W. Brooks, Jr.
IPC分类号： H04J3/06 , H04J3/16 , H04Q11/04 , H05K7/14 , H04J3/02
CPC分类号： H04Q11/0421 , H04J3/1611 , H05K7/1424 , H04J2203/0026 , H04J3/0685
摘要： A universal tributary interface group approach for SONET multiplex equipment in which the shelf is partitioned into regions and each region can be provisioned to support different service types. The universal tributary group system includes an equipment shelf having a backplane. The equipment shelf is partitioned into regions called tributary groups which are each capable of accepting tributary units having compatible bus widths and clock rates. Removable card guides may be inserted into the tributary group spaces so that tributary interface units of different heights and widths may be placed in the tributary group spaces. Additionally, a plurality of bus segments run along the backplane to electrically connect a time slot interchange unit to card slots in the tributary groups. Each of the bus segments is capable of being provisioned to use a bus rate compatible with the data requirements of the tributary group it services.
摘要翻译：一种用于SONET多路复用设备的通用支路接口组方法，其中可以将架子划分为区域，并且每个区域可以被提供以支持不同的服务类型。通用支流组系统包括具有背板的设备架。设备架被划分为称为支流组的区域，每个区域能够接收具有兼容的总线宽度和时钟速率的支路单元。可拆卸的卡片指南可以插入到支流组空间中，使得不同高度和宽度的支流接口单元可以放置在支流组空间中。此外，多个总线段沿着背板延伸，以将时隙交换单元电连接到支路组中的卡槽。每个总线段都能够被配置为使用与其服务的支路组的数据要求兼容的总线速率。

7. 发明授权

US4794604A Optimal error correction method for zero byte time slot interchange (ZBTSI) clear channel data transmission 失效
标题翻译：零字节时隙交换（ZBTSI）的最优纠错方法清除通道数据传输
公开(公告)号：US4794604A
公开(公告)日：1988-12-27
申请号：US67901
申请日：1987-06-30
申请人： Steven S. Gorshe
发明人： Steven S. Gorshe
IPC分类号： H03M5/18 , H04L7/00 , H04L25/49 , H03M13/00 , H04L1/00
CPC分类号： H04L7/0083 , H03M5/18 , H04L25/4925
摘要： A method and circuit for exploiting the characteristics of the ZBTSI algorithm by using the relationship of the data octet and the octets adjacent thereto to detect error conditions such as violations of the DS1 ones density criteria for detection of transmission channel errors in the ZBTSI decoder. This relationship provides an optimized partial error correction technique which minimizes error multiplication in the PCM transmission channels.
摘要翻译：一种通过使用数据八位位组和与其相邻的八位字节的关系来利用ZBTSI算法的特性的方法和电路，用于检测在ZBTSI解码器中用于检测传输信道误差的DS1密度标准的错误条件。该关系提供了优化的部分纠错技术，其使PCM传输信道中的误差乘法最小化。

8. 发明授权

US06690644B1 Mechanism for 1:1, 1+1, and UPSR path-switched protection switching 失效
标题翻译： 1：1，1 + 1和UPSR路径切换保护切换的机制
公开(公告)号：US06690644B1
公开(公告)日：2004-02-10
申请号：US09251975
申请日：1999-02-17
申请人： Steven S. Gorshe
发明人： Steven S. Gorshe
IPC分类号： H04L1226
CPC分类号： H04J3/085 , H04L12/28
摘要： A mechanism for 1:1, 1+1, and UPSR path-switched protection switching, particularly for optical interface units in synchronous optical network (SONET) multiplexer equipment. A working unit and a standby unit pair protect each other in the event of a failure of the working unit or the failure of the span connected to the working unit if both the working and standby units are connected to different spans. Each unit is made responsible for detecting failures of the span that it receives and is primarily responsible for detecting a fault within the unit's own hardware or software. When a unit or span failure is detected, switch control is localized to the two units (i.e. the working and standby unit) which eliminates the need for a third control unit, which reduces processing time and reduces the system hardware. Moreover, this feature allows distributed control of the system protection so that protection switching on multiple unit pairs can be performed in parallel rather than in a serial manner by a common control unit. Both unit and span failures are handled through the same signal pair and simple hardware.
摘要翻译： 1：1，1 + 1和UPSR路由交换保护交换的机制，特别是同步光网络（SONET）多路复用器设备中的光接口单元。如果工作单元和备用单元都连接到不同的跨度，工作单元和备用单元对在工作单元发生故障或连接到工作单元的跨接故障时彼此保护。每个单元负责检测其接收到的跨度的故障，并主要负责检测单元自身硬件或软件中的故障。当检测到单位或跨度故障时，开关控制被定位到两个单元（即工作和备用单元），这消除了对第三控制单元的需要，这减少了处理时间并降低了系统硬件。此外，该特征允许系统保护的分布式控制，使得可以由公共控制单元并行而不是以串行方式执行对多个单元对的保护切换。单位和跨度故障均通过相同的信号对和简单的硬件来处理。

9. 发明授权

US5537632A Method and system for fault coverage testing memory 失效
标题翻译：故障覆盖测试记忆体的方法和系统
公开(公告)号：US5537632A
公开(公告)日：1996-07-16
申请号：US376447
申请日：1995-01-23
申请人： Steven S. Gorshe
发明人： Steven S. Gorshe
IPC分类号： G06F12/16 , G11C29/10 , G11C29/36 , G11C29/00
CPC分类号： G11C29/10 , G11C29/36
摘要： A method for fault coverage testing an integrated circuit having a memory device with word locations, including the steps of setting test data to an initial value, dependently making the test data unique for each of the word locations, and automatically, dependently testing each bit of each of the word locations for a fault using the unique test data which corresponds to the word location being tested. Alternatively, the method may include the steps of inverting a bit of test data, writing the test data to a current word location of the memory device, reading test data from the current word location of the memory device, rotating the test data read by one bit position, repeating the writing, reading and rotating a predetermined number of times for each of the word locations, and comparing the test data read from a last word location of the memory device with a predetermined value. A system for performing the fault coverage testing method is also disclosed.
摘要翻译：一种用于对具有字位置的存储器件的集成电路进行故障覆盖测试的方法，包括将测试数据设置为初始值的步骤，依次使测试数据对于每个单词位置是唯一的，并且自动地依次测试每个位的使用与被测试的单词位置相对应的唯一测试数据来确定故障的每个单词位置。或者，该方法可以包括以下步骤：将测试数据的一位反相，将测试数据写入存储器件的当前字位置，从存储器件的当前字位置读取测试数据，将读取的测试数据旋转一个重复写入，读取和旋转每个单词位置的预定次数，以及将从存储器件的最后一个字位置读取的测试数据与预定值进行比较。还公开了一种用于执行故障覆盖测试方法的系统。

10. 发明授权

US5510786A CMI encoder circuit 失效
标题翻译： CMI编码器电路
公开(公告)号：US5510786A
公开(公告)日：1996-04-23
申请号：US231779
申请日：1994-04-25
申请人： Steven S. Gorshe
发明人： Steven S. Gorshe
IPC分类号： H04L25/49 , H03M5/12
CPC分类号： H04L25/4912
摘要： A Coded Marked Inversion (CMI) encoding circuit having a completely synchronous and digital implementation for encoding a stream of digital data in non-return-to-zero (NRZ) format into the CMI format. The encoding circuit includes a clock for providing a clock signal having a certain period, an input circuit for obtaining two samples of the NRZ data during each clock period, and a state machine which, in response to the two samples of the NRZ data, produces CMI encoded data. In a more advanced implementation, the encoding circuit includes error encoding circuitry for detecting errors in the incoming samples of NRZ data. The encoding circuit then outputs data indicative of the rate at which errors are received.
摘要翻译：具有完全同步和数字实现的编码标记反转（CMI）编码电路，用于将非归零（NRZ）格式的数字数据流编码为CMI格式。编码电路包括用于提供具有一定周期的时钟信号的时钟，用于在每个时钟周期期间获得NRZ数据的两个样本的输入电路，以及响应于NRZ数据的两个样本产生的状态机 CMI编码数据。在更先进的实现中，编码电路包括用于检测NRZ数据的输入采样中的错误的错误编码电路。然后，编码电路输出指示接收错误的速率的数据。

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