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1. 发明申请

US20140156896A1 ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER IDENTIFIER (APIC ID) ASSIGNMENT FOR A MULTI-CORE PROCESSING UNIT 有权
标题翻译：高级可编程中断控制器标识符（APIC ID）多核处理单元的分配
公开(公告)号：US20140156896A1
公开(公告)日：2014-06-05
申请号：US13994104
申请日：2011-12-29
申请人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
发明人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign each active and eligible core a unique advanced programmable interrupt controller (APIC) identifier (ID). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned an APIC ID or as ineligible to be assigned the APIC ID.
摘要翻译：在重新启动或重启包含多核处理器的系统之后，多核处理器可以为每个活动和合格的核心分配唯一的高级可编程中断控制器（APIC）标识符（ID）。初始化逻辑可以将多个处理核心中的每一个的状态检测为活动或不活动。初始化逻辑可以检测多个处理核心中的每个处理核心的属性符合分配APIC ID的资格，或者不符合APIC ID分配的资格。

2. 发明授权

US09658861B2 Boot strap processor assignment for a multi-core processing unit 有权
公开(公告)号：US09658861B2
公开(公告)日：2017-05-23
申请号：US13993310
申请日：2011-12-29
申请人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
发明人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
IPC分类号： G06F9/44 , G06F15/177
CPC分类号： G06F9/4405 , G06F15/177
摘要： Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign one of the cores as a boot strap processor (BSP). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned as a BSP or as ineligible to be assigned as the BSP. The initialization logic may detect a last processing core of the plurality of processing cores in the interconnect that is an active processing core based at least in part on the state and is eligible to be assigned as the BSP based at least in part on the attribute. In various embodiments, the initialization information may assign the last processing core as the BSP.

3. 发明授权

US09372816B2 Advanced programmable interrupt controller identifier (APIC ID) assignment for a multi-core processing unit 有权
标题翻译：用于多核处理单元的高级可编程中断控制器标识符（APIC ID）分配
公开(公告)号：US09372816B2
公开(公告)日：2016-06-21
申请号：US13994104
申请日：2011-12-29
申请人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
发明人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
IPC分类号： G06F13/00 , G06F13/24
CPC分类号： G06F13/24
摘要： Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign each active and eligible core a unique advanced programmable interrupt controller (APIC) identifier (ID). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned an APIC ID or as ineligible to be assigned the APIC ID.
摘要翻译：在重新启动或重启包含多核处理器的系统之后，多核处理器可以为每个活动和合格的核心分配唯一的高级可编程中断控制器（APIC）标识符（ID）。初始化逻辑可以将多个处理核心中的每一个的状态检测为活动或不活动。初始化逻辑可以检测多个处理核心中的每个处理核心的属性符合分配APIC ID的资格，或者不符合APIC ID分配的资格。

4. 发明申请

US20140006767A1 BOOT STRAP PROCESSOR ASSIGNMENT FOR A MULTI-CORE PROCESSING UNIT 有权
标题翻译：用于多核处理单元的引导带处理器分配
公开(公告)号：US20140006767A1
公开(公告)日：2014-01-02
申请号：US13993310
申请日：2011-12-29
申请人： Steven S. Chang , Anshuman Thakur , Ramacharan Charan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
发明人： Steven S. Chang , Anshuman Thakur , Ramacharan Charan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
IPC分类号： G06F9/44
CPC分类号： G06F9/4405 , G06F15/177
摘要： Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign one of the cores as a boot strap processor (BSP). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned as a BSP or as ineligible to be assigned as the BSP. The initialization logic may detect a last processing core of the plurality of processing cores in the interconnect that is an active processing core based at least in part on the state and is eligible to be assigned as the BSP based at least in part on the attribute. In various embodiments, the initialization information may assign the last processing core as the BSP.
摘要翻译：在重新启动或重新启动包括多核处理器的系统之后，多核处理器可以将一个核心分配为引导带处理器（BSP）。初始化逻辑可以将多个处理核心中的每一个的状态检测为活动或不活动。初始化逻辑可以检测多个处理核心中的每一个的属性被认定为被分配为BSP，或者不符合被分配为BSP的资格。初始化逻辑可以至少部分地基于状态来检测作为活动处理核心的互连中的多个处理核心的最后处理核心，并且至少部分地基于该属性将其分配为BSP。在各种实施例中，初始化信息可以将最后的处理核分配为BSP。

5. 发明授权

US09208124B2 Reset of processing core in multi-core processing system 有权
标题翻译：复核处理核心在多核处理系统中
公开(公告)号：US09208124B2
公开(公告)日：2015-12-08
申请号：US13993663
申请日：2011-12-29
申请人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas
发明人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas
IPC分类号： G06F11/00 , G06F15/80 , G06F13/14 , G06F1/24 , G06F11/07
CPC分类号： G06F15/80 , G06F1/24 , G06F11/0709 , G06F11/0724 , G06F11/0757 , G06F13/14
摘要： This disclosure is directed to performing a controlled reset of one or more cores while maintaining operation of at least one other core in a multi-core processor. An initialization core may include reset logic that may detect a problematic core or core that is unresponsive or otherwise not operating properly. The initialization core may generate a packet that enables communication with the problematic core. The initialization core may send a reset packet to the problematic core to instruct the problematic core to perform a reset.
摘要翻译：本公开涉及在多核处理器中保持至少一个其他核的操作的同时执行一个或多个核的受控复位。初始化核心可以包括可以检测无响应的核心或核心的复位逻辑，或者否则其不能正常操作。初始化核心可以生成能够与有问题的核心进行通信的分组。初始化核心可以向有问题的核心发送重置分组，以指示有问题的核心执行复位。

6. 发明授权

US09389657B2 Reset of multi-core processing system 有权
标题翻译：复核多核处理系统
公开(公告)号：US09389657B2
公开(公告)日：2016-07-12
申请号：US13993614
申请日：2011-12-29
申请人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas
发明人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas
IPC分类号： G06F11/00 , G06F1/24 , G06F13/14 , G06F9/44 , G06F1/32
CPC分类号： G06F1/24 , G06F1/3228 , G06F9/4405 , G06F13/14
摘要： An initialization core may include reset logic that may detect a global reset signal (GRS). The initialization core may generate one or more packets that enable communication with the cores. The initialization core may send reset packets to each of the cores that instruct the cores to perform a reset. In some embodiments, the reset command may power-off the cores. The initialization core may then transmit unreset packets to each of the cores that instruct the cores to perform an unreset and power-on the cores. In some embodiments, the cores may resume operation automatically without receipt of the unreset packet. The transmission of the packets may be staggered (staged) to control the power-on of the processor and enable the processor unit to more slowly increase its power state.
摘要翻译：初始化核心可以包括可以检测全局复位信号（GRS）的复位逻辑。初始化核心可以生成一个或多个能够与核心通信的分组。初始化内核可以向指定内核执行复位的每个内核发送复位数据包。在一些实施例中，复位命令可以关闭核心。然后，初始化内核可以将未重新分配的数据包发送到指示内核执行未分配和上电的核心的每个核心。在一些实施例中，核可以自动地恢复运行而不接收未重新分组。分组的传输可以是交错的（分段）以控制处理器的上电，并且使处理器单元能够更慢地增加其功率状态。

7. 发明授权

US09367329B2 Initialization of multi-core processing system 有权
标题翻译：多核处理系统的初始化
公开(公告)号：US09367329B2
公开(公告)日：2016-06-14
申请号：US13993573
申请日：2011-12-29
申请人： Steven S. Chang , Anshuman Thakur , Ramacharan Charan Sundararaman , Ramon Matas
发明人： Steven S. Chang , Anshuman Thakur , Ramacharan Charan Sundararaman , Ramon Matas
IPC分类号： G06F9/24 , G06F15/177 , G06F9/44 , G06F1/24 , G06F11/07 , G06F13/14 , G06F15/80 , G06F12/08 , G06F13/00
CPC分类号： G06F9/4405 , G06F1/24 , G06F9/4403 , G06F11/0724 , G06F12/0813 , G06F13/00 , G06F13/14 , G06F15/177 , G06F15/80
摘要： This disclosure is directed to use of shared initialization and configuration vectors, which are delivered to processing cores in a multi-core processor using packets. An initialization core may include reset logic that may read initialization and configuration vectors from a centralized storage location, which may be on a die containing the processing cores (e.g., a fuse, etc.), off the die (e.g., in volatile memory, flash memory, etc.), or a combination of both. The initialization core may then generate packets to transmit the initialization and configuration vectors to processing cores that await initialization (e.g., following a reset). In some instances, the initialization and configuration vector information may be shared by two or more cores of a same type.
摘要翻译：本公开涉及使用共享的初始化和配置向量，其被传递到使用分组的多核处理器中的处理核心。初始化核心可以包括复位逻辑，其可以从集中存储位置读取初始化和配置向量，集中存储位置可以在包含处理核心（例如，熔丝等）的管芯上，例如在易失性存储器中，闪存等），或两者的组合。初始化内核然后可以生成分组以将初始化和配置向量传送到等待初始化（例如，重置之后）的处理核。在一些情况下，初始化和配置向量信息可以由相同类型的两个或多个核共享。

8. 发明申请

US20140006763A1 INITIALIZATION OF MULTI-CORE PROCESSING SYSTEM 有权
标题翻译：多核处理系统的初始化
公开(公告)号：US20140006763A1
公开(公告)日：2014-01-02
申请号：US13993573
申请日：2011-12-29
申请人： Steven S. Chang , Anshuman Thakur , Ramacharan Charan Sundararaman , Ramon Matas
发明人： Steven S. Chang , Anshuman Thakur , Ramacharan Charan Sundararaman , Ramon Matas
IPC分类号： G06F9/44
CPC分类号： G06F9/4405 , G06F1/24 , G06F9/4403 , G06F11/0724 , G06F12/0813 , G06F13/00 , G06F13/14 , G06F15/177 , G06F15/80
摘要： This disclosure is directed to use of shared initialization and configuration vectors, which are delivered to processing cores in a multi-core processor using packets. An initialization core may include reset logic that may read initialization and configuration vectors from a centralized storage location, which may be on a die containing the processing cores (e.g., a fuse, etc.), off the die (e.g., in volatile memory, flash memory, etc.), or a combination of both. The initialization core may then generate packets to transmit the initialization and configuration vectors to processing cores that await initialization (e.g., following a reset). In some instances, the initialization and configuration vector information may be shared by two or more cores of a same type.
摘要翻译：本公开涉及使用共享的初始化和配置向量，其被传递到使用分组的多核处理器中的处理核心。初始化核心可以包括复位逻辑，其可以从集中存储位置读取初始化和配置向量，集中存储位置可以在包含处理核心（例如，熔丝等）的管芯上，例如在易失性存储器中，闪存等），或两者的组合。初始化内核然后可以生成分组以将初始化和配置向量传送到等待初始化（例如，重置之后）的处理核。在一些情况下，初始化和配置向量信息可以由相同类型的两个或多个核共享。

9. 发明申请

US20140189255A1 METHOD AND APPARATUS TO SHARE MODIFIED DATA WITHOUT WRITE-BACK IN A SHARED-MEMORY MANY-CORE SYSTEM 审中-公开
标题翻译：分享修改数据的方法和设备，无需在共享存储器多核系统中进行回写
公开(公告)号：US20140189255A1
公开(公告)日：2014-07-03
申请号：US13731584
申请日：2012-12-31
申请人： Ramacharan Sundararaman , John C. Mejia , Oscar M. Rosell , Antonio Juan , Ramon Matas
发明人： Ramacharan Sundararaman , John C. Mejia , Oscar M. Rosell , Antonio Juan , Ramon Matas
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0822
摘要： A cache-coherent device may include multiple caches and a cache coherency engine, which monitors whether there are more than one versions of a cache line stored in the caches and whether the version of the cache line in the caches is consistent with the version of the cache line stored in the memory.
摘要翻译：高速缓存一致设备可以包括多个高速缓存和高速缓存一致性引擎，该引擎监视高速缓存中存储的高速缓存行是否存在多于一个版本，高速缓存中的高速缓存行的版本是否与缓存行存储在内存中。

10. 发明申请

US20130268747A1 RESET OF MULTI-CORE PROCESSING SYSTEM 有权
标题翻译：多核处理系统复位
公开(公告)号：US20130268747A1
公开(公告)日：2013-10-10
申请号：US13993614
申请日：2011-12-29
申请人： Steven S. Chang , Anshuman Thakar , Ramacharan Charan Sundararaman , Ramon Matas
发明人： Steven S. Chang , Anshuman Thakar , Ramacharan Charan Sundararaman , Ramon Matas
IPC分类号： G06F1/24
CPC分类号： G06F1/24 , G06F1/3228 , G06F9/4405 , G06F13/14
摘要： An initialization core may include reset logic that may detect a global reset signal (GRS). The initialization core may generate one or more packets that enable communication with the cores. The initialization core may send reset packets to each of the cores that instruct the cores to perform a reset. In some embodiments, the reset command may power-off the cores. The initialization core may then transmit unreset packets to each of the cores that instruct the cores to perform an unreset and power-on the cores. In some embodiments, the cores may resume operation automatically without receipt of the unreset packet. The transmission of the packets may be staggered (staged) to control the power-on of the processor and enable the processor unit to more slowly increase its power state.
摘要翻译：初始化核心可以包括可以检测全局复位信号（GRS）的复位逻辑。初始化核心可以生成一个或多个能够与核心通信的分组。初始化内核可以向指定内核执行复位的每个内核发送复位数据包。在一些实施例中，复位命令可以关闭核心。然后，初始化内核可以将未重新分配的数据包发送到指示内核执行未分配和上电的核心的每个核心。在一些实施例中，核可以自动地恢复运行而不接收未重新分组。分组的传输可以是交错的（分段）以控制处理器的上电，并且使处理器单元能够更慢地增加其功率状态。

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