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1. 发明授权

US5705321A Method for manufacture of quantum sized periodic structures in Si materials 失效
标题翻译：在Si材料中制造量子尺寸周期结构的方法
公开(公告)号：US5705321A
公开(公告)日：1998-01-06
申请号：US490101
申请日：1995-06-06
申请人： Steven R. J. Brueck , An-Shyang Chu , Bruce L. Draper , Saleem H. Zaidi
发明人： Steven R. J. Brueck , An-Shyang Chu , Bruce L. Draper , Saleem H. Zaidi
IPC分类号： G03F7/00 , G03F7/20 , H01L21/027 , H01L21/306 , H01L21/308 , G03C5/00
CPC分类号： B82Y10/00 , G03F7/0035 , G03F7/2022 , G03F7/70408 , G03F7/70466 , H01L21/0274 , H01L21/30608 , H01L21/3088
摘要： Multiple-exposure fine-line interferometric lithography, combined with conventional optical lithography, is used in a sequence of steps to define arrays of complex, nm-scale structures in a photoresist layer. Nonlinearities in the develop, mask etch, and Si etch processes are used to modify the characteristics and further reduce the scale of the structures. Local curvature dependent oxidation provides an additional flexibility. Electrical contact to the quantum structures is achieved. Uniform arrays of Si structures, including quantum wires and quantum dots, are produced that have structure dimensions on the scale of electronic wave functions. Applications include enhanced optical interactions with quantum structured Si, including optical emission and lasing and novel electronic devices based on the fundamentally altered electronic properties of these materials. All of the process sequences involve parallel processing steps to make large fields of these quantum structures. The processes are, further, consistent with modern micro lithographic manufacturing practice, promising inexpensive and large-scale manufacture.
摘要翻译：多次曝光细线干涉光刻技术与传统的光刻技术相结合，被用于一系列步骤，以确定光致抗蚀剂层中复杂的nm尺度结构的阵列。开发，掩模蚀刻和Si蚀刻工艺中的非线性被用于改变特性并进一步减小结构的尺度。局部曲率依赖氧化提供了额外的灵活性。实现与量子结构的电接触。产生了包括量子线和量子点的Si结构的均匀阵列，其具有电子波函数规模的结构尺寸。应用包括与量子结构Si的增强的光学相互作用，包括光发射和激光，以及基于这些材料的基本改变的电子特性的新型电子器件。所有的过程序列都涉及到并行处理步骤，以形成这些量子结构的大场。这些过程进一步与现代微型平版印刷制造实践一致，有希望的廉价和大规模制造。

2. 发明授权

US5830611A Use of diffracted light from latent images in photoresist for optimizing image contrast 失效
$Use of diffracted light from latent images in photoresist for optimizing image contrast$
标题翻译：在光致抗蚀剂中使用来自潜像的衍射光来优化图像对比度
公开(公告)号：US5830611A
公开(公告)日：1998-11-03
申请号：US847618
申请日：1992-03-05
申请人： Kenneth P. Bishop , Lisa M. Milner , S. Sohail H. Naqvi , John R. McNeil , Bruce L. Draper
发明人： Kenneth P. Bishop , Lisa M. Milner , S. Sohail H. Naqvi , John R. McNeil , Bruce L. Draper
IPC分类号： G03F7/20 , G03F7/207
CPC分类号： G03F7/70558 , G03F7/70641 , G03F7/70675
摘要： The present invention includes a method and apparatus for the rapid, nondestructive evaluation of the contrast of a latent image in a photoresist. More particularly, the contrast of the latent image is directly monitored by measuring the intensity of the light diffracted from a pattern in the exposed, undeveloped photoresist known as the latent image. The proper exposure tool parameters, such as exposure tool time and focus, is suitably determined based on the intensity of different orders of diffracted light, namely the 2nd-order diffracted from the latent image. In a preferred embodiment, a test pattern consisting of a periodic pattern, or a pattern of the device associated with the particular lithographic step, is employed to provide well-defined diffraction orders.
摘要翻译：本发明包括用于快速，非破坏性评估光致抗蚀剂中的潜像的对比度的方法和装置。更具体地，潜像的对比度通过测量从曝光的未开发的光致抗蚀剂中被描述为潜像的图案衍射的光的强度来直接监测。适当的曝光工具参数，例如曝光工具的时间和焦点，可以根据不同的衍射光的强度，即从潜像衍射的二阶度来确定。在优选实施例中，使用由周期性图案或与特定光刻步骤相关联的器件的图案组成的测试图案来提供明确定义的衍射级。

3. 发明授权

US06268630B1 Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications 有权
标题翻译：绝缘体上的场效应晶体管，具有改进的体态连接，适用于辐射硬件应用
公开(公告)号：US06268630B1
公开(公告)日：2001-07-31
申请号：US09270374
申请日：1999-03-16
申请人： James R. Schwank , Marty R. Shaneyfelt , Bruce L. Draper , Paul E. Dodd
发明人： James R. Schwank , Marty R. Shaneyfelt , Bruce L. Draper , Paul E. Dodd
IPC分类号： H01L2900
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/78609 , H01L29/78618
摘要： A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.
摘要翻译：公开了绝缘体上硅（SOI）场效应晶体管（FET）及其制造方法。 SOI FET的特征在于仅通过形成晶体管的有源层部分地（例如，大约一半）延伸的源极。此外，最小面积的身体接合触点提供与源的短路电连接以减少浮体效应。身体接触触点提高了晶体管的电气特性，并且还提供了用于地面和空间应用的器件的改进的单事件镦粗（SEU）辐射硬度。与没有特别制备的硬化掩埋氧化物层制造的常规SOI晶体管相比，SOI FET也提供总剂量辐射硬度的改善。可以根据本发明制造互补的n沟道和p沟道SOI FET，以形成用于商业和军事应用的集成电路（IC）。

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