专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08397185B1 Graphical user aid for technology migration and associated methods 有权
标题翻译：用于技术迁移和相关方法的图形用户帮助
公开(公告)号：US08397185B1
公开(公告)日：2013-03-12
申请号：US13461040
申请日：2012-05-01
申请人： Steven Perry , Jinyong Yuan , Shih-Yueh Lin , John R. Chase
发明人： Steven Perry , Jinyong Yuan , Shih-Yueh Lin , John R. Chase
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A graphical user aid that may be used for migrating source devices, such as programmable logic designs (PLDs or FPGAs) into target devices, such as equivalent or substitute application-specific integrated circuits (“ASICs”) is provided. A device selector guide is provided for evaluating migration prospects from the source device to the target device before completing the migration.
摘要翻译：提供了可用于将源设备（例如可编程逻辑设计（PLD或FPGA））迁移到目标设备（诸如等效或替代专用集成电路（ASIC））中的图形用户辅助。提供了一种设备选择器指南，用于在完成迁移之前评估从源设备到目标设备的迁移前景。

2. 发明授权

US08191020B1 Graphical user aid for technology migration and associated methods 有权
标题翻译：用于技术迁移和相关方法的图形用户帮助
公开(公告)号：US08191020B1
公开(公告)日：2012-05-29
申请号：US12612479
申请日：2009-11-04
申请人： Steven Perry , Jinyong Yuan , Shih Yueh Lin , John R. Chase
发明人： Steven Perry , Jinyong Yuan , Shih Yueh Lin , John R. Chase
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A graphical user aid that may be used for migrating source devices, such as programmable logic designs (PLDs or FPGAs) into target devices, such as equivalent or substitute application-specific integrated circuits (“ASICs”) is provided. A device selector guide is provided for evaluating migration prospects from the source device to the target device before completing the migration.
摘要翻译：提供了可用于将源设备（诸如可编程逻辑设计（PLD或FPGA））迁移到目标设备（诸如等效或代替应用专用集成电路（ASIC））中的图形用户辅助。提供了一种设备选择器指南，用于在完成迁移之前评估从源设备到目标设备的迁移前景。

3. 发明授权

US08065128B1 Methods and apparatus for automated testbench generation 失效
标题翻译：自动化测试平台生成的方法和设备
公开(公告)号：US08065128B1
公开(公告)日：2011-11-22
申请号：US10693546
申请日：2003-10-23
申请人： John R. Chase
发明人： John R. Chase
IPC分类号： G06F17/50 , G06F17/00
CPC分类号： G06F17/5054 , G06F17/5045 , G06F2217/14
摘要： Methods and apparatus are provided for efficiently generating designs for testing design automation tools and applications. Randomized and diverse test designs with realistic attributes are automatically generated to allow comprehensive testing of design automation tools such as synthesis, simulation, and place and route tools used to implement designs on electronic devices. Each test design can incorporate a wide range of attributes to allow thorough integration testing of a design automation tool.
摘要翻译：提供了用于有效地生成用于测试设计自动化工具和应用的设计的方法和装置。自动生成具有现实属性的随机和多样化测试设计，以便对设计自动化工具进行全面测试，如综合，仿真以及用于在电子设备上实现设计的位置和路线工具。每个测试设计都可以包含多种属性，以便对设计自动化工具进行彻底的集成测试。

4. 发明授权

US5923077A Passive component integrated circuit chip 失效
标题翻译：无源元件集成电路芯片
公开(公告)号：US5923077A
公开(公告)日：1999-07-13
申请号：US22102
申请日：1998-02-11
申请人： John R. Chase , Bruce Leon Jeppesen
发明人： John R. Chase , Bruce Leon Jeppesen
IPC分类号： H01G4/40 , H01L27/06 , H03H1/02 , H03H7/06 , H01L29/00 , H01L23/48 , H01L23/52
CPC分类号： H01G4/40 , H01L27/0688
摘要： A passive component integrated circuit chip formed on an insulative substrate includes a first conductive metallic layer on a major surface of the substrate; a layer of dielectric material on top of the first conductive metallic layer; a second conductive metallic layer on top of the formation of dielectric material; a layer of insulative material on top of the layer of dielectric material and on and around the second conductive metallic layer, but not completely covering the second conductive metallic layer; a conductive via in contact with a portion of the second conductive metallic layer left uncovered by the layer of insulative material; a resistive layer on top of the layer of insulative material and in contact with the conductive via; a conductive contact in contact with the resistive layer; and a passivation layer on top of the resistive layer so as to provide a seal between the resistive layer and the conductive contact. Conductive end terminations are advantageously formed on the ends of the substrate to terminate selected conductive contacts and/or conductive metallic layers.
摘要翻译：形成在绝缘基板上的无源部件集成电路芯片包括在基板的主表面上的第一导电金属层; 在所述第一导电金属层的顶部上的介电材料层; 在介电材料形成的顶部上的第二导电金属层; 绝缘材料层，位于第二导电金属层上并且在第二导电金属层周围，但不完全覆盖第二导电金属层; 与由绝缘材料层未覆盖的第二导电金属层的一部分接触的导电通孔; 在绝缘材料层顶部并与导电通孔接触的电阻层; 与电阻层接触的导电触点; 以及在电阻层的顶部上的钝化层，以便在电阻层和导电触点之间提供密封。有利地，在基底的端部上形成导电末端以终止所选择的导电接触和/或导电金属层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式