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1. 发明申请

US20130271199A1 VOLTAGE LEVEL SHIFT WITH INTERIM-VOLTAGE-CONTROLLED CONTENTION INTERRUPT 有权
标题翻译：具有电压控制中断的电压水平移位
公开(公告)号：US20130271199A1
公开(公告)日：2013-10-17
申请号：US13997584
申请日：2011-11-14
申请人： Steven K. Hsu , Vinod Sannareddy , Amit Agarwal , Feroze A. Merchant , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Vinod Sannareddy , Amit Agarwal , Feroze A. Merchant , Ram K. Krishnamurthy
IPC分类号： H03L5/00
CPC分类号： H03L5/00 , H03K3/356182 , H03K19/018507
摘要： Methods and systems to implement voltage level shifting with interim-voltage-controlled contention-interruption. A voltage level shifter (VLS) may include voltage level shift circuitry to level shift an input logical state from an input voltage swing to an output voltage swing. The VLS may include contention circuitry, a contention interrupter, and an interrupt controller to generate a contention-interrupt control having an interim voltage swing. A lower limit of the interim voltage swing may correspond to a lower limit of the output voltage swing. An upper limit of the interim voltage swing may correspond to an upper limit of the input voltage swing. The VLS may be implemented to level shift true and complimentary logical states, such as with cascode voltage switch logic (CVSL). The interim-voltage-controlled contention interrupter may help to maintain voltages within process-based voltage reliability limits of the contention interrupter, with relatively little delay, and relatively little power and area consumption.
摘要翻译：通过中压控制争用中断实现电压电平转换的方法和系统。电压电平移位器（VLS）可以包括电压电平移位电路，用于将输入逻辑状态从输入电压摆幅电平移位到输出电压摆幅。 VLS可以包括争用电路，争用中断器和中断控制器，以产生具有临时电压摆幅的争用中断控制。临时电压摆幅的下限可以对应于输出电压摆幅的下限。临时电压摆幅的上限可以对应于输入电压摆幅的上限。可以实现VLS以实现水平移位真实和互补的逻辑状态，例如用共源共栅电压开关逻辑（CVSL）。临时电压控制的争用中断器可能有助于在相对较小的延迟和相对较小的功率和面积消耗的情况下，在竞争中断器的基于过程的电压可靠限度内维持电压。

2. 发明授权

US07209395B2 Low leakage and leakage tolerant stack free multi-ported register file 有权
标题翻译：低泄漏和容错堆栈自由多端口寄存器文件
公开(公告)号：US07209395B2
公开(公告)日：2007-04-24
申请号：US10953202
申请日：2004-09-28
申请人： Steven K. Hsu , Amit Agarwal , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Amit Agarwal , Ram K. Krishnamurthy
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/413 , G11C2207/007
摘要： A device includes a number of memory cells. Each of the memory cells includes a transistor stack coupled to a bit line. A value of a charge on the bit line during an access mode represents a value of data stored in an accessed memory cell. During a non-access mode, all transistors of the transistor stack are turned off to save power. The transistors are turn off regardless of the value of the data stored in the memory cells.
摘要翻译：一种设备包括多个存储单元。每个存储单元包括耦合到位线的晶体管堆叠。访问模式期间位线上的电荷值表示存储在访问存储单元中的数据的值。在非访问模式期间，晶体管堆叠的所有晶体管都被关闭以节省功率。无论存储在存储器单元中的数据的值如何，晶体管都截止。

3. 发明授权

US07855575B1 Wide voltage range level shifter with symmetrical switching 有权
标题翻译：具有对称开关的宽电压范围电平移位器
公开(公告)号：US07855575B1
公开(公告)日：2010-12-21
申请号：US12566977
申请日：2009-09-25
申请人： Steven K. Hsu , Daniel I. Davis , Amit Agarwal , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Daniel I. Davis , Amit Agarwal , Ram K. Krishnamurthy
IPC分类号： H03K19/0175
CPC分类号： H03K3/35613
摘要： Described herein is the method and apparatus for generating symmetrical level shifted signals by a symmetrical level shifter. The symmetrical level shifter comprises an edge detector operable to generate transition edge based pulses from an input signal based on a first power supply level; a voltage level shifter, coupled with the edge detector, operable to convert the transition edge based pulses based on the first power supply level to edge based pulses based on a second power supply level; and a divider circuit, coupled with the voltage level shifter, operable to generate an output signal from the edge based pulses based on the second power supply level.
摘要翻译：这里描述了通过对称电平移位器产生对称电平移位信号的方法和装置。对称电平移位器包括边沿检测器，其可操作以基于第一电源电平从输入信号产生基于过渡沿的脉冲; 与边缘检测器耦合的电压电平移位器可操作以基于第二电源电平将基于第一电源电平的基于边沿的脉冲转换为基于边缘的脉冲; 以及与所述电压电平移位器耦合的分频器电路，用于基于所述第二电源电平从所述基于边沿的脉冲产生输出信号。

4. 发明申请

US20170193376A1 AREA/ENERGY COMPLEX REGULAR EXPRESSION PATTERN MATCHING HARDWARE FILTER BASED ON TRUNCATED DETERMINISTIC FINITE AUTOMATA (DFA) 审中-公开
公开(公告)号：US20170193376A1
公开(公告)日：2017-07-06
申请号：US14989694
申请日：2016-01-06
申请人： Amit Agarwal , Steven K. Hsu , Ram K. Krishnamurthy , Bharan Giridhar
发明人： Amit Agarwal , Steven K. Hsu , Ram K. Krishnamurthy , Bharan Giridhar
IPC分类号： G06N5/04 , G06N7/00
CPC分类号： G06N5/047 , G06F16/90344 , G06N7/005 , H04L63/1416
摘要： A method and apparatus are described for performing complex regex pattern matching utilizing filters based on truncated Deterministic Finite Automata (DFA). For example, one embodiment of a method comprises: representing a set of reference strings as a DFA; truncating the DFA based on a truncating policy, wherein the truncated DFA does not generate a false positive match; creating a filter based on the truncated DFA; filtering an input string against the set of reference strings by running the input string through the filter.

5. 发明授权

US09397641B2 Apparatus and method for low power fully-interruptible latches and master-slave flip-flops 有权
公开(公告)号：US09397641B2
公开(公告)日：2016-07-19
申请号：US14711686
申请日：2015-05-13
申请人： Steven K. Hsu , Amit Agarwal , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Amit Agarwal , Ram K. Krishnamurthy
IPC分类号： H03K3/356 , H03K3/3562
CPC分类号： H03K3/35625 , H03K3/356104
摘要： Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop.

6. 发明申请

US20090168483A1 Ultra low voltage and minimum operating voltage tolerant register file 有权
公开(公告)号：US20090168483A1
公开(公告)日：2009-07-02
申请号：US12006238
申请日：2007-12-31
申请人： Steven K. Hsu , Amit Agarwal , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Amit Agarwal , Ram K. Krishnamurthy
IPC分类号： G11C5/06 , G11C7/00
CPC分类号： G11C11/419
摘要： Methods and apparatus relating ultra-low voltage memory bit cells are described. In an embodiment, an ultra-low voltage memory device is provided using redundant paths to data storage nodes controlled by complementary write word lines. Other embodiments are also described.

7. 发明授权

US09059715B2 Voltage level shift with interim-voltage-controlled contention interrupt 有权
标题翻译：具有临时电压控制争用中断的电压电平偏移
公开(公告)号：US09059715B2
公开(公告)日：2015-06-16
申请号：US13997584
申请日：2011-11-14
申请人： Steven K. Hsu , Vinod Sannareddy , Amit Agarwal , Feroze A. Merchant , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Vinod Sannareddy , Amit Agarwal , Feroze A. Merchant , Ram K. Krishnamurthy
IPC分类号： H03L5/00 , H03K19/0185 , H03K3/356
CPC分类号： H03L5/00 , H03K3/356182 , H03K19/018507
摘要： Methods and systems to implement voltage level shifting with interim-voltage-controlled contention-interruption. A voltage level shifter (VLS) may include voltage level shift circuitry to level shift an input logical state from an input voltage swing to an output voltage swing. The VLS may include contention circuitry, a contention interrupter, and an interrupt controller to generate a contention-interrupt control having an interim voltage swing. A lower limit of the interim voltage swing may correspond to a lower limit of the output voltage swing. An upper limit of the interim voltage swing may correspond to an upper limit of the input voltage swing. The VLS may be implemented to level shift true and complimentary logical states, such as with cascode voltage switch logic (CVSL). The interim-voltage-controlled contention interrupter may help to maintain voltages within process-based voltage reliability limits of the contention interrupter, with relatively little delay, and relatively little power and area consumption.
摘要翻译：通过中压控制争用中断实现电压电平转换的方法和系统。电压电平移位器（VLS）可以包括电压电平移位电路，用于将输入逻辑状态从输入电压摆幅电平移位到输出电压摆幅。 VLS可以包括争用电路，争用中断器和中断控制器，以产生具有临时电压摆幅的争用中断控制。临时电压摆幅的下限可以对应于输出电压摆幅的下限。临时电压摆幅的上限可以对应于输入电压摆幅的上限。可以实现VLS以实现水平移位真实和互补的逻辑状态，例如用共源共栅电压开关逻辑（CVSL）。临时电压控制的争用中断器可能有助于在相对较小的延迟和相对较小的功率和面积消耗的情况下，在竞争中断器的基于过程的电压可靠限度内维持电压。

8. 发明授权

US07800407B1 Multiple voltage mode pre-charging and selective level shifting 有权
标题翻译：多电压模式预充电和选择电平转换
公开(公告)号：US07800407B1
公开(公告)日：2010-09-21
申请号：US12492938
申请日：2009-06-26
申请人： Amit Agarwal , Steven K. Hsu , Ram K. Krishnamurthy
发明人： Amit Agarwal , Steven K. Hsu , Ram K. Krishnamurthy
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521
摘要： To pre-charge a node to one of first and second voltage levels in response to inputs received at the corresponding voltage level, to selectively level shift the node from the first voltage level to the second voltage level when in a first voltage mode, and to maintain the node at the second voltage level when in a second voltage mode. Level shifting from first voltage level may be performed within one gate stage that may be bypassed when in the second voltage mode. The node may be discharged with no delay difference between the first and second voltage modes. Inputs may include a clock signal, which may be received at either of the first and second voltage levels without level shifting the clock signal. A circuit may be implemented with a multi-core processor system to permit selective voltage mode operation of the cores.
摘要翻译：为了响应于在相应电压电平处接收到的输入，将节点预充电到第一和第二电压电平之一，以便当在第一电压模式下选择性地将节点从第一电压电平移位到第二电压电平，并且当处于第二电压模式时，将节点保持在第二电压电平。可以在一个门级内执行从第一电压电平的电平转换，当处于第二电压模式时，可能被旁路。可以在第一和第二电压模式之间没有延迟差放电节点。输入可以包括时钟信号，其可以在第一和第二电压电平中的任何一个处接收，而不会对时钟信号进行电平移位。电路可以用多核处理器系统来实现，以允许芯的选择性电压模式操作。

9. 发明申请

US20090168557A1 Ultra wide voltage range register file circuit using programmable triple stacking 审中-公开
标题翻译：超宽电压范围寄存器文件电路采用可编程三重堆叠
公开(公告)号：US20090168557A1
公开(公告)日：2009-07-02
申请号：US12006276
申请日：2007-12-31
申请人： Amit Agarwal , Steven K. Hsu , Ram K. Krishnamurthy
发明人： Amit Agarwal , Steven K. Hsu , Ram K. Krishnamurthy
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C7/12 , G11C16/08
摘要： Methods and apparatus relating to expanding the operational voltage range of data storage circuits are described. In an embodiment, low voltage data storage circuit operation is improved by driving a transistor with a control word line programmable circuit. Other embodiments are also described.
摘要翻译：描述了扩展数据存储电路的工作电压范围的方法和装置。在一个实施例中，通过用控制字线可编程电路驱动晶体管来提高低电压数据存储电路操作。还描述了其它实施例。

10. 发明授权

US07606062B2 Ultra low voltage and minimum operating voltage tolerant register file 有权
标题翻译：超低电压和最低工作电压容限寄存器文件
公开(公告)号：US07606062B2
公开(公告)日：2009-10-20
申请号：US12006238
申请日：2007-12-31
申请人： Steven K. Hsu , Amit Agarwal , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Amit Agarwal , Ram K. Krishnamurthy
IPC分类号： G11C11/40
CPC分类号： G11C11/419
摘要： Methods and apparatus relating ultra-low voltage memory bit cells are described. In an embodiment, an ultra-low voltage memory device is provided using redundant paths to data storage nodes controlled by complementary write word lines. Other embodiments are also described.
摘要翻译：描述了关于超低电压存储器位单元的方法和装置。在一个实施例中，使用对由互补写入字线控制的数据存储节点的冗余路径提供超低电压存储器件。还描述了其它实施例。

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