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1. 发明申请

US20100094847A1 METHOD AND APPARATUS FOR MULTIPLE-PROTOCOL ACCESS TO OBJECT-BASED STORAGE 审中-公开
标题翻译：多协议访问基于对象的存储的方法和设备
公开(公告)号：US20100094847A1
公开(公告)日：2010-04-15
申请号：US12395767
申请日：2009-03-02
申请人： Steven J. Malan , Frank G. Logan, III , Patrick J. Kelsey , Edward S. Quicksall
发明人： Steven J. Malan , Frank G. Logan, III , Patrick J. Kelsey , Edward S. Quicksall
IPC分类号： G06F17/30
CPC分类号： H04L69/18 , G06F16/972
摘要： In one embodiment, an apparatus includes a storage presentation module and a mapping module in communication with the storage presentation module and an object pool module. The storage presentation module is operable to provide a first storage interface and a second storage interface via a network interface. The first storage interface is associated with a first storage resource accessible via a first storage protocol, and the second storage interface is associated with a second storage resource accessible via a second storage protocol different from the first storage protocol. The mapping module is operable to receive from the storage presentation module a request for access to the first storage resource based on the first storage protocol and a request for access to the second storage resource based on the second storage protocol. The mapping module is operable to convert the request for access to the first storage resource into a request for access to a first object in the object pool module, the first object is associated with the first storage resource. The mapping module is operable to convert the request for access to the second storage resource into a request for access to a second object in the object pool module, the second object is associated with the second storage resource.
摘要翻译：在一个实施例中，一种装置包括与存储呈现模块和对象池模块通信的存储呈现模块和映射模块。存储呈现模块可操作以经由网络接口提供第一存储接口和第二存储接口。第一存储接口与可经由第一存储协议访问的第一存储资源相关联，并且第二存储接口与可通过不同于第一存储协议的第二存储协议访问的第二存储资源相关联。映射模块可操作以基于第一存储协议从存储呈现模块接收对第一存储资源的访问请求，以及基于第二存储协议访问第二存储资源的请求。所述映射模块可操作以将对所述第一存储资源的访问请求转换为对所述对象池模块中的第一对象的访问请求，所述第一对象与所述第一存储资源相关联。所述映射模块可操作以将对所述第二存储资源的访问请求转换为对所述对象池模块中的第二对象的访问请求，所述第二对象与所述第二存储资源相关联。

2. 发明授权

US5905905A System for copying IOBS from FIFO into I/O adapter, writing data completed IOB, and invalidating completed IOB in FIFO for reuse of FIFO 失效
标题翻译：将IOBS从FIFO复制到I / O适配器的系统，写入数据完成IOB，并使完成的IOB在FIFO中无效再次使用FIFO
公开(公告)号：US5905905A
公开(公告)日：1999-05-18
申请号：US906765
申请日：1997-08-05
申请人： Aaron J. Dailey , Kenneth J. Gibson , Jack P. Kroun , Edward S. Quicksall
发明人： Aaron J. Dailey , Kenneth J. Gibson , Jack P. Kroun , Edward S. Quicksall
IPC分类号： G06F13/12 , G06F13/20 , G06F13/28
CPC分类号： G06F13/126
摘要： A host computer having a CPU and a FIFO memory connected to an I/O adapter for the exchange of I/O information between the host and the adapter. The host writes I/O commands and stores them in a relatively small FIFO memory of the host. The I/O commands are then copied to a relatively large I/O memory array in the I/O adapter where they are stored until the I/O command is completed. The FIFO is then free for use by other I/O commands from the host CPU. I/O completion information is returned to a completion queue in the host by the adapter. This information includes completion status and an indication of the number of I/O commands copied to the adapter from the host FIFO. This allows the CPU to invalidate and reuse all FIFO locations containing I/O commands that have been copied from the FIFO to the adapter I/O array.
摘要翻译：主计算机具有连接到I / O适配器的CPU和FIFO存储器，用于在主机和适配器之间交换I / O信息。主机写I / O命令并将其存储在主机的相对较小的FIFO存储器中。然后将I / O命令复制到I / O适配器中存储的相对较大的I / O存储器阵列，直到I / O命令完成。然后FIFO可以从主机CPU的其他I / O命令免费使用。 I / O完成信息由适配器返回到主机中的完成队列。该信息包括完成状态和从主机FIFO复制到适配器的I / O命令的数量的指示。这允许CPU使包含从FIFO复制到适配器I / O阵列的I / O命令的所有FIFO位置无效并重新使用。

3. 发明授权

US06952743B2 Interface for distributed processing of SCSI tasks 有权
标题翻译： SCSI任务的分布式处理接口
公开(公告)号：US06952743B2
公开(公告)日：2005-10-04
申请号：US10794694
申请日：2004-03-05
申请人： William M. Ortega, III , Edward S. Quicksall
发明人： William M. Ortega, III , Edward S. Quicksall
IPC分类号： G06F3/00 , G06F3/06 , G06F13/00 , G06F13/14 , G06F13/28 , G06F13/38 , G06F15/16
CPC分类号： G06F13/387 , G06F3/0613 , G06F3/0635 , G06F3/0659 , G06F3/067
摘要： The SCSI control block interface provides for distributed processing of storage commands that provides transports and processing blocks the ability to interconnect with each other independent of the underlying transport or hardware architecture. The interface receives a SCSI control block from a transport and determines a storage command associated with the SCSI control block. Based upon the storage command, a particular processor that processes the storage command is determined. The SCSI control block is routed to the appropriate processor for processing. After processing, the SCB is routed to a transport for delivery.
摘要翻译： SCSI控制块接口提供存储命令的分布式处理，其提供传输和处理块彼此独立于底层传输或硬件架构互连的能力。接口从传输接收SCSI控制块，并确定与SCSI控制块相关联的存储命令。基于存储命令，确定处理存储命令的特定处理器。 SCSI控制块被路由到适当的处理器进行处理。经过处理后，SCB将路由到运输中以进行交付。

4. 发明授权

US06449289B1 Multi-processor bus protocol system 有权
标题翻译：多处理器总线协议系统
公开(公告)号：US06449289B1
公开(公告)日：2002-09-10
申请号：US09169444
申请日：1998-10-09
申请人： Edward S. Quicksall
发明人： Edward S. Quicksall
IPC分类号： G06F1316
CPC分类号： G06F13/4291
摘要： A method of communicating between first and second controllers (including between processes within the controllers, or microprocessors) on an I2C bus is provided. The I2C bus is of the type which transmits data packets that start with a start condition and end with a stop condition, and that includes a destination address followed by a transmission type, a first data byte, a second data byte, and one or more additional data bytes. The method includes the steps of: designating a destination address with a unique bus address (i.e., devAddress) of the second controller; designating the first data byte with a unique bus address (i.e., ownAddress) of the first controller; and specifying the transmission type, wherein the first and second controllers initiate a master-slave relationship for read and write operations between controllers. The invention also provides an I2C bus protocol system. The system includes an I2C bus with means for communicating an I2C packet across the bus. First and second controllers connect to the bus, with each controller having (a) means for specifying a devAddress as a slave address in the I2C packet, (b) means for specifying ownAddress as a master address in a first data byte of the I2C packet, and (c) means for specifying a tag within a subsequent data byte of the I2C packet, wherein the first and second controllers initiate a master-slave relationship for read and write operations along a conduit between processes within the controllers.
摘要翻译：提供了一种在I2C总线上的第一和第二控制器（包括控制器内的处理或微处理器之间）之间进行通信的方法。 I2C总线是以起始条件开始并以停止条件结束的数据包的类型，其包括目的地地址，后跟传输类型，第一数据字节，第二数据字节和一个或多个附加数据字节。该方法包括以下步骤：用第二控制器的唯一总线地址（即devAddress）指定目的地地址; 用第一控制器的唯一总线地址（即，自己的地址）指定第一数据字节; 并指定所述传输类型，其中所述第一和第二控制器启动用于控制器之间的读和写操作的主 - 从关系。本发明还提供了一种I2C总线协议系统。该系统包括具有用于在总线上通信I2C分组的装置的I2C总线。第一和第二控制器连接到总线，每个控制器具有（a）用于在I2C分组中指定devAddress作为从机地址的装置，（b）在I2C分组的第一数据字节中指定ownAddress作为主地址的装置，以及（c）用于在所述I2C分组的后续数据字节中指定标签的装置，其中所述第一和第二控制器在所述控制器内的进程之间沿着导管进行用于读取和写入操作的主从关系。

5. 发明授权

US06442196B1 Data communications system 失效
标题翻译：数据通信系统
公开(公告)号：US06442196B1
公开(公告)日：2002-08-27
申请号：US09127647
申请日：1998-07-31
申请人： Edward S. Quicksall
发明人： Edward S. Quicksall
IPC分类号： H04L516
CPC分类号： H04L5/16
摘要： The invention includes a method for transferring user data between a first data communications device and a second data communications device over a data link. The first data communications device transmits a DLE-BEL to the second data communications device to request initialization. The second data communications device transmits a DLE-SI to the first data communications device in response to the DLE-BEL to indicate initialization to receive the user data. The first data communications device transmits a DLE-STX to the second data communications device in response to the DLE-SI to identify the start of a frame of user data. The first data communications device transmits at least a portion of the user data to the second data communications device after transmitting the DLE-STX. The first data communications device transmits a frame-ending control code to the second data communications device after transmitting the user data. The frame-ending control code is either a DLE-ETB, DLE-ETX, or DLE-ESC. A DLE-ETB indicates an end to the frame with more frames to come. A DLE-ETX indicates an end to the frame and to the data transaction. A DLE-ESC indicates an end to the frame and a line-turn. The first data communications device transmits check values to the second data communications device. The second data communications device transmits a DLE-p or a DLE-a to the first data communications device in response to processing the check values to acknowledge that the frame of user data is error-free.
摘要翻译：本发明包括一种通过数据链路在第一数据通信设备和第二数据通信设备之间传送用户数据的方法。第一数据通信设备将DLE-BEL发送到第二数据通信设备以请求初始化。第二数据通信设备响应于DLE-BEL将DLE-SI发送到第一数据通信设备以指示初始化以接收用户数据。第一数据通信设备响应于DLE-SI将DLE-STX发送到第二数据通信设备以识别用户数据帧的开始。在发送DLE-STX之后，第一数据通信设备将至少一部分用户数据发送到第二数据通信设备。第一数据通信设备在发送用户数据之后向第二数据通信设备发送帧结束控制码。帧结束控制代码是DLE-ETB，DLE-ETX或DLE-ESC。 DLE-ETB表示框架结束，帧数将更多。 DLE-ETX表示帧和数据事务的结束。 DLE-ESC表示帧的结束和线转。第一数据通信设备向第二数据通信设备发送检查值。第二数据通信设备响应于处理检查值来向第一数据通信设备发送DLE-p或DLE-a，以确认用户数据帧是无错误的。

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