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1. 发明申请

US20100207208A1 NANOWIRE MESH DEVICE AND METHOD OF FABRICATING SAME 有权
公开(公告)号：US20100207208A1
公开(公告)日：2010-08-19
申请号：US12371943
申请日：2009-02-17
申请人： Stephen W. Bedell , Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffery W. Sleight
发明人： Stephen W. Bedell , Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffery W. Sleight
IPC分类号： H01L29/78 , H01L21/336 , H01L21/302
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66772 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/78696 , Y10S977/72 , Y10S977/742 , Y10S977/762 , Y10S977/938
摘要： A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region.

2. 发明授权

US07893492B2 Nanowire mesh device and method of fabricating same 有权
标题翻译：纳米线网装置及其制造方法
公开(公告)号：US07893492B2
公开(公告)日：2011-02-22
申请号：US12371943
申请日：2009-02-17
申请人： Stephen W. Bedell , Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
发明人： Stephen W. Bedell , Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
IPC分类号： H01L21/02
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66772 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/78696 , Y10S977/72 , Y10S977/742 , Y10S977/762 , Y10S977/938
摘要： A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region.
摘要翻译：提供一种半导体结构，其包括位于衬底表面上的多个垂直堆叠且垂直间隔开的半导体纳米线（例如，半导体纳米线网）。每个垂直堆叠和垂直间隔开的半导体纳米线的一个端段连接到源极区域，并且每个垂直堆叠和垂直间隔开的半导体纳米线的另一个端部段连接到漏极区域。包括栅极电介质和栅极导体的栅极区域邻接多个垂直堆叠和垂直间隔的半导体纳米线，并且源极区域和漏极区域与栅极区域自对准。

3. 发明申请

US20100297816A1 NANOWIRE MESH DEVICE AND METHOD OF FABRICATING SAME 有权
标题翻译：纳米丝网装置及其制造方法
公开(公告)号：US20100297816A1
公开(公告)日：2010-11-25
申请号：US12848582
申请日：2010-08-02
申请人： Stephen W. Bedell , Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
发明人： Stephen W. Bedell , Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
IPC分类号： H01L21/336
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66772 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/78696 , Y10S977/72 , Y10S977/742 , Y10S977/762 , Y10S977/938
摘要： A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region.
摘要翻译：提供一种半导体结构，其包括位于衬底表面上的多个垂直堆叠且垂直间隔开的半导体纳米线（例如，半导体纳米线网）。每个垂直堆叠和垂直间隔开的半导体纳米线的一个端段连接到源极区域，并且每个垂直堆叠和垂直间隔开的半导体纳米线的另一个端部段连接到漏极区域。包括栅极电介质和栅极导体的栅极区域邻接多个垂直堆叠和垂直间隔的半导体纳米线，并且源极区域和漏极区域与栅极区域自对准。

4. 发明授权

US07892945B2 Nanowire mesh device and method of fabricating same 有权
公开(公告)号：US07892945B2
公开(公告)日：2011-02-22
申请号：US12848582
申请日：2010-08-02
申请人： Stephen W. Bedell , Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
发明人： Stephen W. Bedell , Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
IPC分类号： H01L21/76
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66772 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/78696 , Y10S977/72 , Y10S977/742 , Y10S977/762 , Y10S977/938
摘要： A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region.

5. 发明授权

US08399933B2 Semiconductor device having silicon on stressed liner (SOL) 有权
标题翻译：在应力衬垫（SOL）上具有硅的半导体器件
公开(公告)号：US08399933B2
公开(公告)日：2013-03-19
申请号：US13365764
申请日：2012-02-03
申请人： Stephen W. Bedell , Josephine B. Chang , Chung-Hsun Lin
发明人： Stephen W. Bedell , Josephine B. Chang , Chung-Hsun Lin
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66477 , H01L21/8238 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/6653 , H01L29/66628 , H01L29/66651 , H01L29/66772 , H01L29/7843 , H01L29/7849
摘要： A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner.
摘要翻译：公开了一种制造集成电路的方法和在应力衬垫上具有硅的集成电路。在一个实施例中，该方法包括提供包括嵌入式一次性层的半导体衬底，以及去除该一次性层的至少一部分以在衬底内形成空隙。该方法还包括在该空隙中沉积材料以形成应力衬垫，以及在衬底的外部半导体层上形成晶体管。该半导体层将晶体管与应力衬垫分开。在一个实施例中，衬底包括隔离区; 并且所述去除包括在所述隔离区域中形成凹部，以及经由所述凹部去除所述一次性层的至少一部分。在一个实施例中，沉积包括通过凹部将材料沉积在空隙中。端盖可以形成在应力衬垫的端部处的凹部中。

6. 发明申请

US20120199941A1 SEMICONDUCTOR DEVICE HAVING SILICON ON STRESSED LINER (SOL) 有权
标题翻译：应力衬里上的硅半导体器件（SOL）
公开(公告)号：US20120199941A1
公开(公告)日：2012-08-09
申请号：US13365764
申请日：2012-02-03
申请人： Stephen W. Bedell , Josephine B. Chang , Chung-Hsun Lin
发明人： Stephen W. Bedell , Josephine B. Chang , Chung-Hsun Lin
IPC分类号： H01L29/06
CPC分类号： H01L29/66477 , H01L21/8238 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/6653 , H01L29/66628 , H01L29/66651 , H01L29/66772 , H01L29/7843 , H01L29/7849
摘要： A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner.
摘要翻译：公开了一种制造集成电路的方法和在应力衬垫上具有硅的集成电路。在一个实施例中，该方法包括提供包括嵌入式一次性层的半导体衬底，以及去除该一次性层的至少一部分以在衬底内形成空隙。该方法还包括在该空隙中沉积材料以形成应力衬垫，以及在衬底的外部半导体层上形成晶体管。该半导体层将晶体管与应力衬垫分开。在一个实施例中，衬底包括隔离区; 并且所述去除包括在所述隔离区域中形成凹部，以及经由所述凹部去除所述一次性层的至少一部分。在一个实施例中，沉积包括通过凹部将材料沉积在空隙中。端盖可以形成在应力衬垫的端部处的凹部中。

7. 发明授权

US08138523B2 Semiconductor device having silicon on stressed liner (SOL) 有权
标题翻译：在应力衬垫（SOL）上具有硅的半导体器件
公开(公告)号：US08138523B2
公开(公告)日：2012-03-20
申请号：US12575962
申请日：2009-10-08
申请人： Stephen W. Bedell , Josephine B. Chang , Chung-Hsun Lin
发明人： Stephen W. Bedell , Josephine B. Chang , Chung-Hsun Lin
IPC分类号： H01L21/8238
CPC分类号： H01L29/66477 , H01L21/8238 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/6653 , H01L29/66628 , H01L29/66651 , H01L29/66772 , H01L29/7843 , H01L29/7849
摘要： A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner.
摘要翻译：公开了一种制造集成电路的方法和在应力衬垫上具有硅的集成电路。在一个实施例中，该方法包括提供包括嵌入式一次性层的半导体衬底，以及去除该一次性层的至少一部分以在衬底内形成空隙。该方法还包括在该空隙中沉积材料以形成应力衬垫，以及在衬底的外部半导体层上形成晶体管。该半导体层将晶体管与应力衬垫分开。在一个实施例中，衬底包括隔离区; 并且所述去除包括在所述隔离区域中形成凹部，以及经由所述凹部去除所述一次性层的至少一部分。在一个实施例中，沉积包括通过凹部将材料沉积在空隙中。端盖可以形成在应力衬垫的端部处的凹部中。

8. 发明申请

US20110084315A1 SEMICONDUCTOR DEVICE HAVING SILICON ON STRESSED LINER (SOL) 有权
标题翻译：应力衬里上的硅半导体器件（SOL）
公开(公告)号：US20110084315A1
公开(公告)日：2011-04-14
申请号：US12575962
申请日：2009-10-08
申请人： Stephen W. Bedell , Josephine B. Chang , Chung-Hsun Lin
发明人： Stephen W. Bedell , Josephine B. Chang , Chung-Hsun Lin
IPC分类号： H01L27/08 , H01L21/30
CPC分类号： H01L29/66477 , H01L21/8238 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/6653 , H01L29/66628 , H01L29/66651 , H01L29/66772 , H01L29/7843 , H01L29/7849
摘要： A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner.
摘要翻译：公开了一种制造集成电路的方法和在应力衬垫上具有硅的集成电路。在一个实施例中，该方法包括提供包括嵌入式一次性层的半导体衬底，以及去除该一次性层的至少一部分以在衬底内形成空隙。该方法还包括在该空隙中沉积材料以形成应力衬垫，以及在衬底的外部半导体层上形成晶体管。该半导体层将晶体管与应力衬垫分开。在一个实施例中，衬底包括隔离区; 并且所述去除包括在所述隔离区域中形成凹部，以及经由所述凹部去除所述一次性层的至少一部分。在一个实施例中，沉积包括通过凹部将材料沉积在空隙中。端盖可以形成在应力衬垫的端部处的凹部中。

9. 发明授权

US09059073B2 Method for controlled removal of a semiconductor device layer from a base substrate 有权
标题翻译：从基底基板控制去除半导体器件层的方法
公开(公告)号：US09059073B2
公开(公告)日：2015-06-16
申请号：US13603944
申请日：2012-09-05
申请人： Stephen W. Bedell , Cheng-Wei Cheng , Devendra K. Sadana , Kuen-Ting Shiu , Norma E. Sosa Cortes
发明人： Stephen W. Bedell , Cheng-Wei Cheng , Devendra K. Sadana , Kuen-Ting Shiu , Norma E. Sosa Cortes
IPC分类号： H01L21/20 , H01L21/18 , H01L21/78 , H01L21/02 , H01L31/18
CPC分类号： H01L21/187 , H01L21/02002 , H01L21/7813 , H01L31/1892 , Y02E10/50
摘要： A method of removing a semiconductor device layer from a base substrate is provided that includes providing a crack propagation layer on an upper surface of a base substrate. A semiconductor device layer including at least one semiconductor device is formed on the crack propagation layer. Next, end portions of the crack propagation layer are etched to initiate a crack in the crack propagation layer. The etched crack propagation layer is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate. The cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate.
摘要翻译：提供从基底基板去除半导体器件层的方法，其包括在基底基板的上表面上提供裂纹扩展层。在裂纹扩展层上形成包括至少一个半导体器件的半导体器件层。接下来，蚀刻裂纹扩展层的端部以在裂纹扩展层中引发裂纹。蚀刻的裂纹扩展层然后被切割，以向半导体器件层的表面和另一个裂开的裂纹扩展层部分提供切割的裂纹扩展层部分到基底衬底的上表面。从半导体器件层的表面去除切割的裂纹扩展层部分，并从基底基板的上表面除去另一个裂开的裂纹扩展层部分。

10. 发明授权

US08927318B2 Spalling methods to form multi-junction photovoltaic structure 有权
标题翻译：形成多结光伏结构的剥落方法
公开(公告)号：US08927318B2
公开(公告)日：2015-01-06
申请号：US13160067
申请日：2011-06-14
申请人： Stephen W. Bedell , Devendra K. Sadana , Davood Shahrjerdi
发明人： Stephen W. Bedell , Devendra K. Sadana , Davood Shahrjerdi
IPC分类号： H01L31/0216 , H01L21/18 , H01L21/02 , H01L21/304 , H01L31/0687 , H01L31/18
CPC分类号： H01L31/074 , H01L21/02532 , H01L21/02535 , H01L21/0262 , H01L21/304 , H01L31/0304 , H01L31/0312 , H01L31/0687 , H01L31/06875 , H01L31/0725 , H01L31/0745 , H01L31/075 , H01L31/076 , H01L31/1808 , H01L31/1852 , H01L31/1892 , Y02E10/544 , Y02P70/521
摘要： A method cleaving a semiconductor material that includes providing a germanium substrate having a germanium and tin alloy layer is present therein. A stressor layer is deposited on a surface of the germanium substrate. A stress from the stressor layer is applied to the germanium substrate, in which the stress cleaves the germanium substrate to provide a cleaved surface. The cleaved surface of the germanium substrate is then selective to the germanium and tin alloy layer of the germanium substrate. In another embodiment, the germanium and tin alloy layer may function as a fracture plane during a spalling method.
摘要翻译：一种切割半导体材料的方法，其中包括提供具有锗和锡合金层的锗衬底。应力层沉积在锗衬底的表面上。来自应力层的应力施加到锗衬底，其中应力切割锗衬底以提供切割表面。然后，锗衬底的切割表面对锗衬底的锗和锡合金层是选择性的。在另一个实施例中，锗和锡合金层可以在剥落方法中用作断裂面。

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