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    • 4. 发明申请
    • Spectral Selective Solar Control Film Containing an Air Layer for Windows
    • 含有空气层的光谱选择性太阳能控制膜
    • US20110013273A1
    • 2011-01-20
    • US12762486
    • 2010-04-19
    • Stephen S. WilsonBart WilsonSeth Wilson
    • Stephen S. WilsonBart WilsonSeth Wilson
    • G02B5/26B32B37/12
    • G02B5/26B32B7/06B32B17/10
    • A building structure having a high efficiency solar control system is provided. The building structure may have a window defined by a sheet of glass and a film mounted to its exterior side. There may be a gap between the film and the glass wherein the film, film and gap, or gap provides thermal insulation. The film may reflect solar radiation in the near and mid infrared ranges yet allow high transmission of light in the visible range such that the occupants of the building structure may view his/her surroundings through the window. The film may have a layer of silver which reflects the solar radiation in the near and mid infrared ranges. Since the silver is susceptible to oxidation and turns the silver into a black body which absorbs the near and mid infrared radiation, a protective layer on the exterior of the infrared reflecting layer may be designed to slow the rate of oxidation of the silver layer to an acceptable level. The silver layer may be sandwiched between the glass which does not allow oxygen to diffuse there through and reach the layer of silver and the protective layer having a certain thickness which slows down the rate of oxygen diffusion to an acceptable level.
    • 提供了具有高效太阳能控制系统的建筑结构。 建筑结构可以具有由玻璃板和安装到其外侧的膜限定的窗口。 膜和玻璃之间可能存在间隙,其中膜,膜和间隙或间隙提供热绝缘。 该影片可以在近红外范围和中红外范围内反射太阳辐射,但允许在可见光范围内的高透射率,使得建筑结构的乘客可以通过窗户观看他/她的周围环境。 该膜可以具有在近红外范围和中红外范围内反射太阳辐射的一层银。 由于银易于氧化并且将银变成吸收近红外辐射和中红外辐射的黑体,所以红外反射层外部的保护层可被设计成将银层的氧化速率降低到 可接受水平 银层可以夹在玻璃之间,玻璃不允许氧在其中扩散并到达银层,并且具有一定厚度的保护层将氧扩散速率降低到可接受的水平。
    • 5. 发明授权
    • Phased array antenna having reduced beam settling times and related methods
    • 具有减小的光束稳定时间的相控阵天线和相关方法
    • US06690324B2
    • 2004-02-10
    • US09991495
    • 2001-11-09
    • David Kenyon VailFrank J. TaborDaniel P. BlomStephen S. Wilson
    • David Kenyon VailFrank J. TaborDaniel P. BlomStephen S. Wilson
    • H01Q322
    • H01Q1/38H01Q3/26H01Q3/36
    • A phased array antenna may include a substrate and a plurality of phased array antenna elements carried by the substrate. The phased array antenna may also include a plurality of antenna element controllers for the phased array antenna elements and a central controller for providing beam steering commands and edge trigger synchronization signals for the antenna element controllers. Furthermore, each of the antenna element controllers may store a respective next beam steering command and implement the respective next beam steering command as a respective active beam steering command responsive to the edge trigger synchronization signal from the central controller. The edge trigger synchronization signal may be delivered substantially simultaneously to all of the antenna element controllers, and each antenna element controller may detect the edge trigger synchronization pulse only during a predetermined time window, for example.
    • 相控阵天线可以包括衬底和由衬底承载的多个相控阵天线元件。 相控阵天线还可以包括用于相控阵天线元件的多个天线元件控制器和用于为天线元件控制器提供波束控制命令和边沿触发同步信号的中央控制器。 此外,每个天线元件控制器可以存储相应的下一个波束转向命令,并且响应于来自中央控制器的边沿触发同步信号,实现相应的下一个波束控制指令作为相应的主动波束操纵指令。 边缘触发同步信号可以基本上同时发送到所有天线元件控制器,并且每个天线元件控制器可以仅在预定时间窗口期间检测边缘触发同步脉冲。
    • 8. 发明授权
    • Serial pipelined phase weight generator for phased array antenna having
subarray controller delay equalization
    • 用于具有子阵列控制器延迟均衡的相控阵天线的串行流水线相位重量发生器
    • US5990830A
    • 1999-11-23
    • US138417
    • 1998-08-24
    • David K. VailMark D. FisherStephen S. Wilson
    • David K. VailMark D. FisherStephen S. Wilson
    • H01Q3/22H01Q3/26H01Q21/00
    • H01Q3/22H01Q21/0006H01Q3/2694
    • A "just in time" pipelined signal processing architecture for a phased array antenna simultaneously updates the weights of all phase control elements of the antenna with reduced wiring complexity and fast beam steering updates. Signal propagation paths between a pipelined communication link--through subarray control processors distributed along the pipeline link--and phase control elements of the antenna array are provided with respectively different serial pipelined transport delays. These delays are such that all phase control signals produced by the subarray control processors are applied simultaneously to their associated subsets of antenna phase control elements. The use of serial (FIFO) delays to equalize pipeline and weight processing latency allows each subarray controller to process and forward serial beam vector data at the same data rate at which it is received from an upstream host processor.
    • 用于相控阵天线的“即时”流水线信号处理架构同时以降低的布线复杂性和快速波束转向更新来更新天线的所有相位控制元件的权重。 沿着管线链路分布的流水线通信子阵列控制处理器和天线阵列的相位控制元件之间的信号传播路径分别被提供有不同的串行流水线传输延迟。 这些延迟使得由子阵列控制处理器产生的所有相位控制信号同时应用于其相关的天线相位控制元件的子集。 使用串行(FIFO)延迟来均衡流水线和权重处理延迟允许每个子阵列控制器以与上游主机处理器相同的数据速率处理和转发串行波束矢量数据。
    • 10. 发明授权
    • Pipeline processor
    • US4524455A
    • 1985-06-18
    • US269143
    • 1981-06-01
    • Wlodzimierz HolsztynskiStephen S. Wilson
    • Wlodzimierz HolsztynskiStephen S. Wilson
    • G06F15/80G06T1/20G06K9/36
    • G06T1/20G06F15/8015
    • A system particularly suited for serially processing spatially oriented data such as data matrices includes a plurality of serially connected processing cells for performing a number of successive, different operations on the data using pipeline processing techniques. In one embodiment, each unit cell comprises a memory in the form of a shift register for storing data received from the neighboring, upstream cell. The data is transferred from the memory to a time delaying storage medium such as a latch and to a processing circuit which operates on the data and provides data output to the neighboring, downstream cell. In another embodiment, a simple parallel-in, parallel-out latch is employed as the cell memory thereby allowing the processing circuit to simultaneously access all of the data stored in memory. Data is output from the latch in pre-determined groups and is multiplexed to one portion of the processing circuit. One of the data groups output from the latch is delayed by a shift register and then delivered to another portion of the processing circuit which selectively receives data from the first portion. A central controller connected to each cell controls the transfer of data within and between the cells.