专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07924281B2 System and method for determining illumination of a pixel by shadow planes 有权
标题翻译：用于通过阴影平面确定像素的照明的系统和方法
公开(公告)号：US07924281B2
公开(公告)日：2011-04-12
申请号：US10906852
申请日：2005-03-09
申请人： Stephen L. Morein , Larry D. Seiler , Michael Doggett , Jocelyn Houle
发明人： Stephen L. Morein , Larry D. Seiler , Michael Doggett , Jocelyn Houle
IPC分类号： G06T15/50
CPC分类号： G06T15/50 , G06T15/005 , G06T15/60 , G06T15/80 , G06T2215/12
摘要： A graphics processing circuit includes a pixel shader operative to provide pixel color information in response to image data representing a scene to be rendered; a texture circuit, coupled to the pixel shader, operative to determine a luminance value to be applied to a pixel of interest based on the luminance values of the pixels that define a plane including the pixel of interest; and a render back end circuit, coupled to the texture circuit, operative to compute the luminance values from a shadow map that specifies the distance from the light source of the nearest object at a plurality of locations. A pixel illumination method includes receiving color information for a pixel to be rendered, defining a plane containing at least one pixel of interest, the plane including a plurality of planar values; comparing the plurality of planar values to a corresponding set of distance values; determining a luminance value for the at least one pixel of interest; and applying the luminance value to the at least one pixel of interest.
摘要翻译：图形处理电路包括像素着色器，用于响应于表示要渲染的场景的图像数据而提供像素颜色信息; 耦合到像素着色器的纹理电路，用于基于限定包括感兴趣像素的平面的像素的亮度值来确定要施加到感兴趣像素的亮度值; 以及耦合到纹理电路的渲染后端电路，用于从阴影图计算亮度值，所述阴影贴图指定在多个位置处距离最近物体的光源的距离。像素照明方法包括：接收要渲染的像素的颜色信息，定义包含至少一个感兴趣像素的平面，所述平面包括多个平面值; 将所述多个平面值与相应的一组距离值进行比较; 确定所述感兴趣的所述至少一个像素的亮度值; 以及将所述亮度值应用于所述至少一个感兴趣的像素。

2. 发明授权

US07978194B2 Method and apparatus for hierarchical Z buffering and stenciling 有权
标题翻译：用于分级Z缓冲和模板的方法和装置
公开(公告)号：US07978194B2
公开(公告)日：2011-07-12
申请号：US10790953
申请日：2004-03-02
申请人： Larry D. Seiler , Stephen L. Morein
发明人： Larry D. Seiler , Stephen L. Morein
IPC分类号： G06T15/40 , G06T15/50 , G06T1/00 , G09G5/02
CPC分类号： G06T15/405
摘要： A method and apparatus for hierarchical Z buffering stenciling includes comparing an input tile Z value range with a hierarchical Z value range and a stencil code. The method and apparatus also updates the hierarchical Z value range and stencil code in response the comparison and determines whether to render a plurality of pixels within the input tile based on the comparison of the input tile Z value range with the hierarchical Z value range and stencil code. In determining whether to render the tile, a stencil test and a hierarchical Z value test is performed. If one of the test fails, the tile is killed as it is determined that the pixels are not visible in the graphical output. If the stencil test passes and the hierarchical Z test passes, the pixels within the tile are rendered, as it is determined that the pixels may be visible.
摘要翻译：用于分层Z缓冲模板的方法和装置包括将输入图块Z值范围与分层Z值范围和模版代码进行比较。所述方法和装置还响应于比较而更新分层Z值范围和模板代码，并且基于输入瓦片Z值范围与分层Z值范围和模板的比较来确定是否在输入瓦片内呈现多个像素码。在确定是否渲染图块时，执行模板测试和分层Z值测试。如果其中一个测试失败，那么瓷砖将被杀死，因为确定像素在图形输出中不可见。如果模板测试通过并且层次化Z测试通过，则图块内的像素被渲染，因为确定像素可以是可见的。

3. 发明授权

US07538765B2 Method and apparatus for generating hierarchical depth culling characteristics 有权
标题翻译：用于产生分层深度剔除特征的方法和装置
公开(公告)号：US07538765B2
公开(公告)日：2009-05-26
申请号：US10914949
申请日：2004-08-10
申请人： Larry D. Seiler , Laurent Lefebvre , Stephen L. Morein
发明人： Larry D. Seiler , Laurent Lefebvre , Stephen L. Morein
IPC分类号： G06T15/40
CPC分类号： G06T15/40
摘要： A method and apparatus for generating hierarchical depth culling characteristics includes determining a first minimum depth value and a first maximum depth value for a first graphical element. The graphical element may be a primitive. The first minimum depth value may be a minimum Z-plane depth of a pixel within the primitive and a first maximum depth value is a maximum Z-plane value for a pixel within the primitive. The method and apparatus further includes determining a second minimum depth value and a second maximum depth value for a second graphical element, which may be a tile. The method and apparatus further includes calculating an intersection depth range having an intersection minimum depth value and an intersection maximum depth value based on the intersection of the first minimum depth value and the first maximum depth value and the second minimum depth value and the second maximum depth value.
摘要翻译：一种用于产生分级深度剔除特征的方法和装置包括确定第一图形元素的第一最小深度值和第一最大深度值。图形元素可以是基元。第一最小深度值可以是基元内的像素的最小Z平面深度，并且第一最大深度值是该图元内的像素的最大Z平面值。所述方法和装置还包括确定可以是瓦片的第二图形元素的第二最小深度值和第二最大深度值。该方法和装置还包括基于第一最小深度值和第一最大深度值与第二最小深度值和第二最大深度的交点来计算具有交点最小深度值和交叉最大深度值的交点深度范围值。

4. 发明授权

US07336284B2 Two level cache memory architecture 有权
标题翻译：两级缓存内存架构
公开(公告)号：US07336284B2
公开(公告)日：2008-02-26
申请号：US10820580
申请日：2004-04-08
申请人： Stephen L. Morein , Michael Doggett
发明人： Stephen L. Morein , Michael Doggett
IPC分类号： G06T11/40 , G09G5/00 , G09G5/36
CPC分类号： G06F12/0897 , G06F3/14 , G06T1/60 , G09G2360/121 , G09G2360/125 , G09G2360/126
摘要： A memory architecture for use in a graphics processor including a main memory, a level one (L1) cache and a level two (L2) cache, coupled between the main memory and the L1 cache is disclosed. The L2 cache stores overlapping requests to the main memory before the requested information is stored in the L1 cache. In this manner, overlapping requests for previously stored information is retrieved from the faster L2 cache as opposed to the relatively slower main memory.
摘要翻译：公开了一种用于图形处理器的存储器架构，包括主存储器，第一级（L1）高速缓存和第二层（L2）高速缓存，耦合在主存储器和L1高速缓存之间。在将所请求的信息存储在L1高速缓存中之前，L2高速缓存将重叠请求存储到主存储器。以这种方式，与较慢的主存储器相比，从更快的L2高速缓存中检索先前存储的信息的重叠请求。

5. 发明申请

US20090086563A1 Memory Word Line Driver Featuring Reduced Power Consumption 有权
标题翻译：具有降低功耗的内存字线驱动器
公开(公告)号：US20090086563A1
公开(公告)日：2009-04-02
申请号：US11865342
申请日：2007-10-01
申请人： Stephen L. Morein
发明人： Stephen L. Morein
IPC分类号： G11C8/10
CPC分类号： G11C8/08 , G11C8/06
摘要： Embodiments of a random access memory word line driver circuit that reduces consumption of standby power are described. The word line driver is based on NOR-gate logic in which, for memory array consisting of a plurality of memory cells and word line drivers, given two inputs selected one word line goes high and the rest remain zero. The decoder circuit comprises two PMOS transistors in series with an NMOS-based inverter circuit. This arrangement reduces the leakage current through the NMOS transistor when the word line is not selected. An array of word line drivers incorporating a NOR-based decoder includes a shared pull up PMOS transistor for one of two address lines. The shared pull-up PMOS transistor is manufactured to a size on the order of at least two times the width of the remaining transistors of each word line stage.
摘要翻译：描述了降低待机功率消耗的随机存取字字驱动电路的实施例。字线驱动器基于NOR门逻辑，其中对于由多个存储器单元和字线驱动器组成的存储器阵列，给定两个输入，一个字线被选择为高，其余保持为零。解码器电路包括与基于NMOS的反相器电路串联的两个PMOS晶体管。当不选择字线时，这种布置减少了通过NMOS晶体管的漏电流。结合了基于NOR的解码器的字线驱动器阵列包括用于两个地址线之一的共享上拉PMOS晶体管。共享上拉PMOS晶体管的制造尺寸为每个字线级的剩余晶体管的宽度的至少两倍。

6. 发明授权

US07109987B2 Method and apparatus for dual pass adaptive tessellation 有权
标题翻译：用于双通道自适应细分的方法和装置
公开(公告)号：US07109987B2
公开(公告)日：2006-09-19
申请号：US10790952
申请日：2004-03-02
申请人： Vineet Goel , Stephen L. Morein , Robert Scott Hartog
发明人： Vineet Goel , Stephen L. Morein , Robert Scott Hartog
IPC分类号： G06T15/30
CPC分类号： G06T17/20 , G06T15/005 , G06T2200/28
摘要： A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.
摘要翻译：用于双通道适应性镶嵌的方法和装置包括可操作地耦合以接收原始信息的顶点石斑鱼细分器和索引列表以及耦合到顶点石斑鱼细分器的着色器处理单元。在第一次通过期间，着色器处理单元接收从原始信息生成的原始索引和多个基元索引中的每一个的自动索引值。所述方法和装置还包括可操作地耦合到着色器序列的多个顶点着色器输入暂存寄存器，其中多个顶点着色器输入暂存寄存器耦合到多个顶点着色器，使得响应于着色器序列输出，顶点着色器产生细分因素。将细分因子提供给顶点分组器细分器，使得顶点分割器细分器在第二遍期间生成每个进程向量输出，每个基元输出和每个分组输出。

7. 发明授权

US06999076B2 System, method, and apparatus for early culling 有权
标题翻译：用于早期淘汰的系统，方法和装置
公开(公告)号：US06999076B2
公开(公告)日：2006-02-14
申请号：US10076350
申请日：2002-02-19
申请人： Stephen L. Morein
发明人： Stephen L. Morein
IPC分类号： G06T15/40
CPC分类号： G06T15/405 , G06T2200/28
摘要： A method of graphics processing includes determining a non-depth conditional status and an occlusion status of a fragment. Such a method may be used in culling occluded fragments before expending resources such as processing cycles and memory bus usage. In one example, a scratchpad stores depth values of robust fragments and is used for occlusion testing. Graphics architectures, and methods that include use of representative Z values, are also disclosed.
摘要翻译：图形处理的方法包括确定片段的非深度条件状态和遮挡状态。这样的方法可以在消耗诸如处理周期和存储总线使用之类的资源之前用于剔除封闭的片段。在一个示例中，暂存器存储鲁棒片段的深度值，并用于遮挡测试。还公开了包括使用代表性的Z值的图形架构和方法。

8. 发明授权

US06900812B1 Logic enhanced memory and method therefore 有权
标题翻译：因此，逻辑增强的存储器和方法
公开(公告)号：US06900812B1
公开(公告)日：2005-05-31
申请号：US09630784
申请日：2000-08-02
申请人： Stephen L. Morein
发明人： Stephen L. Morein
IPC分类号： G06T15/00 , G09G5/36 , G09G5/39 , G09G5/399
CPC分类号： G09G5/363 , G06T15/005 , G09G5/39 , G09G2340/10
摘要： A logic enhanced memory that may be used in a video graphics system is presented. The logic enhanced memory includes an operation block that performs a number of operations on a block-by-block basis such that parallel processing results. The operations performed by the operation pipeline include blending operations for fragment blocks received from a graphics processing circuit, where the fragment blocks include pixel fragments generated by rendering graphics primitives. Other operations include selective reads and writes to the memory array, clearing functions, and swapping functions. Mask values included in the commands executed to control the operation pipeline allow for selectivity with respect to portions of the data packets, or blocks, to which the operations are applied.
摘要翻译：提出了可以在视频图形系统中使用的逻辑增强存储器。逻辑增强存储器包括一个操作块，该操作块在逐块的基础上执行多个操作以使得并行处理结果。由操作流程执行的操作包括从图形处理电路接收的片段块的混合操作，其中片段块包括通过渲染图形基元生成的像素片段。其他操作包括对存储器阵列的选择性读取和写入，清除功能和交换功能。控制操作流水线所执行的命令中包含的掩码值允许对应用操作的数据包或块的部分进行选择性。

9. 发明授权

US06532515B1 Method and apparatus for performing selective data reads from a memory 有权
标题翻译：用于从存储器执行选择性数据读取的方法和装置
公开(公告)号：US06532515B1
公开(公告)日：2003-03-11
申请号：US09630914
申请日：2000-08-02
申请人： Stephen L. Morein
发明人： Stephen L. Morein
IPC分类号： G06F1200
CPC分类号： G06F13/4243
摘要： A method and apparatus for performing selective data reads from a memory are presented. A memory command is received from a requesting entity, and a memory address is derived from the memory command. The memory address is then applied to a memory array that stores a plurality of data packets, where the memory array outputs a selected data packet in response to the memory address. Data selection control information is also derived from the memory command. The data selection control information is used to select a selected portion of the selected data packet. This selected portion is then packed into at least one data flit, which is sent over a bus to the requesting entity.
摘要翻译：提出了一种用于从存储器执行选择性数据读取的方法和装置。从请求实体接收存储器命令，并且从存储器命令导出存储器地址。然后将存储器地址应用于存储多个数据分组的存储器阵列，其中存储器阵列响应于存储器地址输出所选择的数据分组。数据选择控制信息也从存储器命令得出。数据选择控制信息用于选择所选数据分组的选定部分。然后将该选择的部分打包成至少一个数据传输，其通过总线发送到请求实体。

10. 发明授权

US06452602B1 Method and apparatus for storing compressed data 有权
标题翻译：用于存储压缩数据的方法和装置
公开(公告)号：US06452602B1
公开(公告)日：2002-09-17
申请号：US09459809
申请日：1999-12-13
申请人： Stephen L. Morein
发明人： Stephen L. Morein
IPC分类号： G06T900
CPC分类号： H04N19/12 , H04N19/152 , H04N19/176 , H04N19/423 , H04N19/46
摘要： A method and apparatus for storing data for a plurality of data blocks in a compressed format in memory is presented where the compression scheme used for compressing the data blocks may vary. For each data block included in the plurality of data blocks, the data block is compressed using a compression scheme that is included in a set of predetermined compression schemes. The resulting compressed data set is of a size included in a set of predetermined sizes that correspond to the particular compression scheme utilized. The compressed data set for each block is then stored in a compressed data set memory, where the compressed data sets are stored in groups. A descriptor data set corresponding to each group is then stored in a descriptor memory, where the descriptor data set includes an encoded compression descriptor for each data block included in the group. The data descriptor set also stores a base address that corresponds to a starting location for that group in the compressed data set memory. The encoded compression descriptor for each data block encodes the compression scheme used for that data block and the resulting compressed data set size. When the data for a particular data block is required in an uncompressed format, the storage location of the compressed data set corresponding to that block can be determined from the descriptor data set for the group that includes the particular block required. By combining the base address within the descriptor data set with the sizes of all of the compressed data blocks in the group that precede the particular block in the compressed data set memory, the address for the compressed data set required for decompression can be determined. The compressed data set can then be fetched from memory and decompressed based on the compression scheme as determined from the encoded compression descriptor corresponding to that data block.
摘要翻译：在存储器中以压缩格式存储多个数据块的数据的方法和装置被呈现，其中用于压缩数据块的压缩方案可以变化。对于包括在多个数据块中的每个数据块，使用包含在一组预定压缩方案中的压缩方案来压缩数据块。所得到的压缩数据集具有包含在与所使用的特定压缩方案相对应的一组预定大小中的大小。然后将每个块的压缩数据集存储在压缩数据集存储器中，其中压缩数据集被分组存储。然后将对应于每个组的描述符数据集存储在描述符存储器中，其中描述符数据集包括用于组中包括的每个数据块的编码压缩描述符。数据描述符集还存储与压缩数据集存储器中该组的起始位置相对应的基地址。每个数据块的编码压缩描述符对用于该数据块的压缩方案和所得到的压缩数据集大小进行编码。当以未压缩格式需要特定数据块的数据时，可以从包括所需特定块的组的描述符数据集确定对应于该块的压缩数据集的存储位置。通过将描述符数据集中的基地址与压缩数据组存储器中特定块之前的组中的所有压缩数据块的大小组合，可以确定解压缩所需的压缩数据集的地址。然后可以从存储器取出压缩数据集，并且基于从对应于该数据块的编码压缩描述符确定的压缩方案进行解压缩。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式