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1. 发明申请

US20060080467A1 Apparatus and method for high performance data content processing 审中-公开
标题翻译：用于高性能数据内容处理的装置和方法
公开(公告)号：US20060080467A1
公开(公告)日：2006-04-13
申请号：US10927967
申请日：2004-08-26
申请人： Stephen Gould , Ernest Peltzer , Sean Clift , Kellie Marks , Robert Barrie
发明人： Stephen Gould , Ernest Peltzer , Sean Clift , Kellie Marks , Robert Barrie
IPC分类号： G06F15/16
CPC分类号： G06F9/5005 , G06F2209/509
摘要： Incoming data streams are processed at relatively high speed for decoding, content inspection and classification. A multitude of processing channels process multiple data streams concurrently so as to allows networking based host systems to provide the data streams—as the packets carrying these data streams are received from the network—without requiring the data streams to be buffered. Moreover, host systems processing stored content, such as email messages and computer files, can process more than one stream at once and thereby make better utilization of the host system's CPU. Processing bottlenecks are alleviated by offloading the tasks of data extraction, inspection and classification from the host CPU. A content processing system which so processes the incoming data streams, is readily extensible to accommodate and perform additional data processing algorithms. The content processing system is configurable to enable additional data processing algorithms to be performed in parallel or in series.
摘要翻译：进入数据流以相对高的速度进行处理，用于解码，内容检查和分类。多个处理通道同时处理多个数据流，以便允许基于网络的主机系统提供数据流，因为从网络接收携带这些数据流的分组，而不需要缓冲数据流。此外，处理诸如电子邮件消息和计算机文件的存储内容的主机系统可以一次处理多个流，从而更好地利用主机系统的CPU。通过从主机CPU卸载数据提取，检查和分类的任务，可以减轻处理瓶颈。处理输入数据流的内容处理系统易于扩展以适应并执行附加的数据处理算法。内容处理系统可配置为使得能够并行或串行地执行附加数据处理算法。

2. 发明申请

US20060193159A1 Fast pattern matching using large compressed databases 审中-公开
标题翻译：使用大型压缩数据库的快速模式匹配
公开(公告)号：US20060193159A1
公开(公告)日：2006-08-31
申请号：US11326131
申请日：2006-01-04
申请人： Teewoon Tan , Stephen Gould , Darren Williams , Ernest Peltzer , Robert Barrie
发明人： Teewoon Tan , Stephen Gould , Darren Williams , Ernest Peltzer , Robert Barrie
IPC分类号： G11C15/00
CPC分类号： G06F16/9014
摘要： A pattern matching system includes, in part, a multitude of databases each configured to store and supply compressed data for matching to the received data. The system divides each data stream into a multitude of segments and optionally computes a data pattern from the data stream prior to the division into a multitude of segments. Segments of the data pattern are used to define an address for one or more memory tables. The memory tables are read such that the outputs of one or more memory tables are used to define the address of another memory table. If during any matching cycle, the data retrieved from any of the successively accessed memory tables include an identifier related to any or all previously accessed memory tables, a matched state is detected. A matched state contains information related to the memory location at which the match occurs as well as information related to the matched pattern, such as the match location in the input data stream.
摘要翻译：模式匹配系统部分地包括多个数据库，每个数据库被配置为存储和提供压缩数据以匹配所接收的数据。该系统将每个数据流划分成多个段，并且可选地在分割成多个段之前从数据流计算数据模式。数据模式的段用于定义一个或多个存储表的地址。读取存储器表，使得一个或多个存储器表的输出用于定义另一个存储器表的地址。如果在任何匹配周期期间，从任何连续访问的存储器表中检索的数据包括与任何或所有先前访问的存储器表相关的标识符，则检测到匹配状态。匹配状态包含与匹配发生的存储器位置有关的信息以及与匹配模式相关的信息，例如输入数据流中的匹配位置。

3. 发明申请

US20050035784A1 Apparatus and method for large hardware finite state machine with embedded equivalence classes 有权
标题翻译：具有嵌入式等价类的大型硬件有限状态机的装置和方法
公开(公告)号：US20050035784A1
公开(公告)日：2005-02-17
申请号：US10850978
申请日：2004-05-21
申请人： Stephen Gould , Ernest Peltzer , Robert Barrie , Michael Flanagan , Darren Williams
发明人： Stephen Gould , Ernest Peltzer , Robert Barrie , Michael Flanagan , Darren Williams
IPC分类号： G06F20060101 , G06F7/38 , G06F9/44 , G06F17/50 , H01L20060101
CPC分类号： G06F9/4498
摘要： A programmable finite state machine (FSM) includes, in part, a first address calculation logic block, a first lookup table, a second address calculation logic block, and a second lookup table. The first address calculation logic block generates an address for the first lookup table based on the received input symbol and the current state. The data stored in first look-up table at the generated address is used by the second address calculation logic block to compute an address for the second lookup table. Data stored in the second lookup table is the next state to which the FSM transitions. The programmable FSMs uses redundant information of the transition table to compress these transitions and thus requires a smaller memory while maintaining a high data throughput. The data in the first and second lookup tables are coded and supplied by a compiler. The FSM operation may optionally be pipelined.
摘要翻译：可编程有限状态机（FSM）部分地包括第一地址计算逻辑块，第一查找表，第二地址计算逻辑块和第二查找表。第一地址计算逻辑块基于接收到的输入符号和当前状态生成第一查找表的地址。存储在生成地址的第一查找表中的数据由第二地址计算逻辑块用于计算第二查找表的地址。存储在第二查找表中的数据是FSM转换到的下一个状态。可编程FSM使用过渡表的冗余信息来压缩这些转换，因此需要较小的存储器，同时保持较高的数据吞吐量。第一和第二查找表中的数据由编译器编码和提供。 FSM操作可以可选地被流水线化。

4. 发明申请

US20060184556A1 Compression algorithm for generating compressed databases 审中-公开
标题翻译：用于生成压缩数据库的压缩算法
公开(公告)号：US20060184556A1
公开(公告)日：2006-08-17
申请号：US11326123
申请日：2006-01-04
申请人： Teewoon Tan , Stephen Gould , Darren Williams , Ernest Peltzer , Robert Barrie
发明人： Teewoon Tan , Stephen Gould , Darren Williams , Ernest Peltzer , Robert Barrie
IPC分类号： G06F17/00
CPC分类号： H03M7/30 , G06F16/9014
摘要： A data compressor performing the compression algorithm compresses an original uncompressed pattern database to form an associated compressed pattern database configured for fast retrieval and verification. For each data pattern, the data compressor stores a data in an address of a first memory table and that is defined by a first segment of a group of bits associated with the data pattern. The data compressor stores a second data in an address of a second memory table and that is defined by a second segment of the group of bits associated with the data pattern and further defined by the first data stored in the first memory.
摘要翻译：执行压缩算法的数据压缩器压缩原始未压缩模式数据库以形成配置用于快速检索和验证的相关联的压缩模式数据库。对于每个数据模式，数据压缩器将数据存储在第一存储器表的地址中，并且由与数据模式相关联的一组位的第一段定义。数据压缩器将第二数据存储在第二存储器表的地址中，并且由与数据模式相关联的位组的第二段定义，并由存储在第一存储器中的第一数据进一步限定。

5. 发明授权

US07180328B2 Apparatus and method for large hardware finite state machine with embedded equivalence classes 有权
标题翻译：具有嵌入式等价类的大型硬件有限状态机的装置和方法
公开(公告)号：US07180328B2
公开(公告)日：2007-02-20
申请号：US10850978
申请日：2004-05-21
申请人： Stephen Gould , Ernest Peltzer , Robert Matthew Barrie , Michael Flanagan , Darren Williams
发明人： Stephen Gould , Ernest Peltzer , Robert Matthew Barrie , Michael Flanagan , Darren Williams
IPC分类号： H03K19/173 , G06F7/38
CPC分类号： G06F9/4498
摘要： A programmable finite state machine (FSM) includes, in part, a first address calculation logic block, a first lookup table, a second address calculation logic block, and a second lookup table. The first address calculation logic block generates an address for the first lookup table based on the received input symbol and the current state. The data stored in first look-up table at the generated address is used by the second address calculation logic block to compute an address for the second lookup table. Data stored in the second lookup table is the next state to which the FSM transitions. The programmable FSMs uses redundant information of the transition table to compress these transitions and thus requires a smaller memory while maintaining a high data throughput. The data in the first and second lookup tables are coded and supplied by a compiler. The FSM operation may optionally be pipelined.
摘要翻译：可编程有限状态机（FSM）部分地包括第一地址计算逻辑块，第一查找表，第二地址计算逻辑块和第二查找表。第一地址计算逻辑块基于接收到的输入符号和当前状态生成第一查找表的地址。存储在生成地址的第一查找表中的数据由第二地址计算逻辑块用于计算第二查找表的地址。存储在第二查找表中的数据是FSM转换到的下一个状态。可编程FSM使用过渡表的冗余信息来压缩这些转换，因此需要较小的存储器，同时保持较高的数据吞吐量。第一和第二查找表中的数据由编译器编码和提供。 FSM操作可以可选地被流水线化。

6. 发明申请

US20070230445A1 Integrated Circuit Apparatus And Method For High Throughput Signature Based Network Applications 审中-公开
标题翻译：基于高吞吐量签名的网络应用的集成电路设备及方法
公开(公告)号：US20070230445A1
公开(公告)日：2007-10-04
申请号：US11539607
申请日：2006-10-06
申请人： Robert Barrie , Stephen Gould , Darren Williams , Nicholas de Jong
发明人： Robert Barrie , Stephen Gould , Darren Williams , Nicholas de Jong
IPC分类号： H04L12/66
CPC分类号： H04L65/601 , H04L63/0236 , H04L63/0245
摘要： An architecture for an integrated circuit apparatus and method that allows significant performance improvements for signature based network applications. In various embodiments the architecture allows high throughput classification of packets into network streams, packet reassembly of such streams, filtering and pre-processing of such streams, pattern matching on header and payload content of such streams, and action execution based upon rule-based policy for multiple network applications, simultaneously at wire speed. The present invention is improved over the prior art designs, in performance, flexibility and pattern database size.
摘要翻译：用于集成电路装置和方法的架构，其允许基于签名的网络应用程序的显着性能改进。在各种实施例中，架构允许分组进入网络流的高吞吐量分类，这样的流的分组重组，对这些流的过滤和预处理，这些流的报头和有效载荷内容上的模式匹配以及基于规则的策略的动作执行对于多个网络应用，同时以线速度。在现有技术设计中，在性能，灵活性和模式数据库大小方面改进了本发明。

7. 发明申请

US20070162972A1 Apparatus and method for processing of security capabilities through in-field upgrades 审中-公开
标题翻译：通过现场升级处理安全能力的装置和方法
公开(公告)号：US20070162972A1
公开(公告)日：2007-07-12
申请号：US11330973
申请日：2006-01-11
申请人： Teewoon Tan , Simon Ratner , Darren Williams , Stephen Gould , Robert Barrie
发明人： Teewoon Tan , Simon Ratner , Darren Williams , Stephen Gould , Robert Barrie
IPC分类号： G06F12/14
CPC分类号： G06F21/76 , G06F2221/2111
摘要： A method for upgrading one or more security applications, e.g., anti-spam, anti-virus, intrusion detection/prevention. The method includes deriving a second hardware logic from a security knowledge base. The method includes operating a computing system including a security device. The computer system is coupled to the one or more computer networks, e.g., local area networks, wide area networks, Internet. The security device has one or more security logic processors, which include one or more respective first hardware logic. The method transfers an FPGA image representative of at least the second hardware logic through the computer network to one or more first memory devices. The method includes temporarily halting one or more of the security logic processors at a predetermined portion of the stream of information according to a specific embodiment. The method includes loading the second hardware logic onto the one or more security logic processors while the one or more security logic processors have been paused. The method resumes the operation of the one or more security logic processors.
摘要翻译：一种用于升级一个或多个安全应用的方法，例如反垃圾邮件，防病毒，入侵检测/预防。该方法包括从安全知识库导出第二硬件逻辑。该方法包括操作包括安全设备的计算系统。计算机系统耦合到一个或多个计算机网络，例如局域网，广域网，因特网。安全设备具有一个或多个安全逻辑处理器，其包括一个或多个相应的第一硬件逻辑。该方法将表示至少第二硬件逻辑的FPGA图像通过计算机网络传送到一个或多个第一存储器件。该方法包括根据具体实施例暂时停止信息流的预定部分处的一个或多个安全逻辑处理器。该方法包括在一个或多个安全逻辑处理器已经暂停时将第二硬件逻辑加载到一个或多个安全逻辑处理器上。该方法恢复一个或多个安全逻辑处理器的操作。

8. 发明申请

US20060174343A1 Apparatus and method for acceleration of security applications through pre-filtering 审中-公开
标题翻译：通过预过滤加速安全应用的装置和方法
公开(公告)号：US20060174343A1
公开(公告)日：2006-08-03
申请号：US11291524
申请日：2005-11-30
申请人： Peter Duthie , Peter Bisroev , Teewoon Tan , Darren Williams , Robert Barrie , Stephen Gould
发明人： Peter Duthie , Peter Bisroev , Teewoon Tan , Darren Williams , Robert Barrie , Stephen Gould
IPC分类号： G06F12/14
CPC分类号： G06F21/554 , G06F21/56 , G06F21/562 , G06F21/564 , G06Q10/107 , H04L51/12 , H04L63/1416 , H04L63/1441 , H04L63/145
摘要： A first security processing stage performs a first multitude of tasks and a second security processing stage performs a second multitude of tasks. The first and second multitude of tasks may include common tasks. The first security processing stage is a prefilter to the second security processing stage. The input data received as a data stream is first processed by the first security processing stage, which in response, generates one or more first processed data streams. The first processed data streams may be further processed by the second security processing stage or may bypass the second security processing stage. The first security processing stage operates at a speed greater than the speed of the second security processing stage.
摘要翻译：第一安全处理阶段执行第一多个任务，第二安全处理阶段执行第二大量任务。第一和第二个任务可能包括常见任务。第一安全处理阶段是到第二安全处理阶段的预过滤器。作为数据流接收的输入数据首先由第一安全处理阶段进行处理，第一安全处理阶段响应地生成一个或多个第一处理数据流。第一处理数据流可以由第二安全处理级进一步处理，或可以绕过第二安全处理级。第一安全处理级以大于第二安全处理级的速度的速度操作。

9. 发明申请

US20060085389A1 Method for transformation of regular expressions 审中-公开
标题翻译：正则表达式转换的方法
公开(公告)号：US20060085389A1
公开(公告)日：2006-04-20
申请号：US11213622
申请日：2005-08-26
申请人： Michael Flanagan , Darren Williams , Stephen Gould , Robert Barrie , Teewoon Tan
发明人： Michael Flanagan , Darren Williams , Stephen Gould , Robert Barrie , Teewoon Tan
IPC分类号： G06F17/30 , G06F7/00
CPC分类号： G06F16/90344 , H04L63/1416 , H04L63/145
摘要： A method and apparatus for transforming regular expressions into a less resource intensive representation is disclosed. The method and apparatus converts a collection of regular expressions into a multi-level representation in which the memory requirements of the lowest level representation is reduced when compared with a conventional finite state automaton representation. The method and apparatus converts a collection of regular expressions into a collection of segments and a higher level representation in a way that retains the semantics of the original set of regular expressions. This transformation is performed through the use of an intermediate form. The resulting representation and collection admit an implementation which avoids the potentially costly memory requirements of a traditional implementation of the original expressions.
摘要翻译：公开了一种用于将正则表达式转换为较少资源密集型表示的方法和装置。该方法和装置将正则表达式的集合转换为与常规有限状态自动机表示相比最低级表示的存储器要求减小的多级表示。该方法和装置以保持原始正则表达式集的语义的方式将正则表达式的集合转换为段的集合和较高级表示。这种转换是通过使用中间形式进行的。所得到的表示和集合承认了一种实现，其避免了原始表达式的传统实现的潜在昂贵的存储器需求。

10. 发明申请

US20050028114A1 Efficient representation of state transition tables 有权
标题翻译：状态转换表的有效表示
公开(公告)号：US20050028114A1
公开(公告)日：2005-02-03
申请号：US10850979
申请日：2004-05-21
申请人： Stephen Gould , Robert Barrie , Michael Flanagan , Darren Williams
发明人： Stephen Gould , Robert Barrie , Michael Flanagan , Darren Williams
IPC分类号： G06F20060101 , G06F7/38 , G06F9/44 , G06F17/50 , H01L20060101
CPC分类号： G06F9/4498
摘要： The states associated with a programmable state machine are reordered to compress the storage of transitions which define the state machine. To reorder the states, a score is computed and assigned to each of the states. Next, the states are sorted according to their computed scores. In some embodiments, to compute the score for each current state based on the received input symbol, the number of times that the input symbol causes transition to similar states is added. The sum of the scores in each row of the table is representative of the score for the associated current state associated with that row. The states are sorted according to their score and a new state transition table is generated in accordance with the reordered states.
摘要翻译：与可编程状态机相关联的状态被重新排序以压缩定义状态机的转换的存储。要重新排序状态，计算得分并分配给每个状态。接下来，根据它们的计算分数对状态进行排序。在一些实施例中，为了基于接收到的输入符号来计算每个当前状态的得分，输入符号引起转变到类似状态的次数被增加。表中每行的分数之和表示与该行相关联的当前状态的分数。状态根据其分数进行排序，并根据重新排列的状态生成新的状态转换表。

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