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1. 发明授权

US5812437A Programmable logic unit for arithmetic, logic and equality functions 失效
标题翻译：用于算术，逻辑和等效功能的可编程逻辑单元
公开(公告)号：US5812437A
公开(公告)日：1998-09-22
申请号：US541562
申请日：1995-10-10
申请人： Stephen C. Purcell , John Sheldon Thomson
发明人： Stephen C. Purcell , John Sheldon Thomson
IPC分类号： G06F7/575 , G06F7/50 , G06F7/04
CPC分类号： G06F7/575
摘要： An arithmetic logic unit is disclosed herein which overcomes problems in the art discussed above. In accordance with the present invention, an ALU includes a plurality of individual programmable logic units which selectively implement arithmetic, logic, and equality comparison operations. One bit of each of two or more input signals is provided to respective ones of the logic units. One of a plurality of function signals, each of which being set equal to the truth table for a particular arithmetic, logic, or equality operation, is selectably provided to each of the logic units. Each of the logic units multiplexes the function signal provided thereto according to the particular bits of the input signals received therein to generate first and second output signals. These first and second output signals provided by each of the logic units are combined in an adder such that the resulting bit pattern represents the selected arithmetic, logic, or equality operation of the two or more input signals.
摘要翻译：本文公开了克服上述技术中的问题的算术逻辑单元。根据本发明，ALU包括选择性地执行算术，逻辑和等式比较操作的多个单独的可编程逻辑单元。两个或多个输入信号中的每一个的一位被提供给逻辑单元中的相应的一个。多个功能信号中的一个被选择性地提供给每个逻辑单元，每个功能信号被设置为等于特定算术，逻辑或相等操作的真值表。每个逻辑单元根据其中接收的输入信号的特定比特复用提供给它的功能信号，以产生第一和第二输出信号。由每个逻辑单元提供的这些第一和第二输出信号在加法器中组合，使得所得到的位模式表示两个或更多个输入信号的选择的算术，逻辑或等效运算。

2. 发明授权

US5719802A Adder circuit incorporating byte boundaries 失效
标题翻译：加法器电路并入字节边界
公开(公告)号：US5719802A
公开(公告)日：1998-02-17
申请号：US577032
申请日：1995-12-22
申请人： Stephen C. Purcell , John Sheldon Thomson
发明人： Stephen C. Purcell , John Sheldon Thomson
IPC分类号： G06F7/50 , G06F7/508
CPC分类号： G06F7/508 , G06F2207/382 , G06F2207/5063
摘要： In accordance with the present invention, an adder is disclosed which combines byte boundary control signals with propagate-generate signal pairs immediately resulting from bit pairs of the input signals. Combining the byte boundary control signals with the first level propagate-generate signal pairs, rather than combining the byte boundary control signals with propagate-generate signal pairs indicative of the carry-out of a byte, allows the adder to utilize a more efficient tree signal path topology in which multiple levels of circuitry may be eliminated, thereby resulting in a reduction in propagation delay.
摘要翻译：根据本发明，公开了一种加法器，其将字节边界控制信号与由输入信号的位对立即产生的传播产生信号对组合。将字节边界控制信号与第一级传播产生信号对相结合，而不是将字节边界控制信号与指示字节进位的传播产生信号对相组合，允许加法器利用更有效的树信号路径拓扑，其中可以消除多个电路级，从而导致传播延迟的减小。

3. 发明申请

US20160296747A1 INFLATABLE INTRAVASCULAR ELECTRODE SUPPORTS FOR NEUROMODULATION 审中-公开
标题翻译：用于神经修复的可激活的血管内电极支持
公开(公告)号：US20160296747A1
公开(公告)日：2016-10-13
申请号：US14681036
申请日：2015-04-07
申请人： Richard A. Glenn , Stephen C. Purcell
发明人： Richard A. Glenn , Stephen C. Purcell
IPC分类号： A61N1/05
CPC分类号： A61N1/0551 , A61N1/0558
摘要： An intravascular catheter is positionable within a blood vessel for use in transvenous stimulation of targets external to the wall of the blood vessel. The catheter includes a catheter body, a support at the distal end of the catheter body, and a plurality of electrodes carried by the support. At least a portion of the support being inflatable within the blood vessel to bias at least a portion of the plurality of electrodes into contact with the blood vessel wall.
摘要翻译：血管内导管可定位在血管内，用于静脉刺激血管壁外的靶。导管包括导管主体，在导管主体的远端处的支撑件和由支撑件承载的多个电极。所述支撑体的至少一部分在所述血管内是可充气的，以将所述多个电极的至少一部分偏置成与所述血管壁接触。

4. 发明申请

US20110283293A1 Method and Apparatus for Dynamic Allocation of Processing Resources 有权
标题翻译：处理资源动态分配的方法与装置
公开(公告)号：US20110283293A1
公开(公告)日：2011-11-17
申请号：US13190253
申请日：2011-07-25
申请人： Korbin Van Dyke , Paul Campbell , Don Van Dyke , Ali Alasti , Stephen C. Purcell
发明人： Korbin Van Dyke , Paul Campbell , Don Van Dyke , Ali Alasti , Stephen C. Purcell
IPC分类号： G06F9/50
CPC分类号： G06F9/5044
摘要： A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using available processing resources to produce resulting data, and the resulting data is passed to an input/output device.
摘要翻译：一种用于动态分配处理资源和任务的方法和装置，包括多媒体任务。任务排队，识别可用的处理资源，并在任务之间分配可用的处理资源。可用的处理资源具有与任务相对应的功能程序。使用可用的处理资源执行任务以产生结果数据，并将所得到的数据传递到输入/输出设备。

5. 发明申请

US20100122262A1 Method and Apparatus for Dynamic Allocation of Processing Resources 有权
标题翻译：处理资源动态分配的方法与装置
公开(公告)号：US20100122262A1
公开(公告)日：2010-05-13
申请号：US12688562
申请日：2010-01-15
申请人： Korbin Van Dyke , Paul Campbell , Don Van Dyke , Ali Alasti , Stephen C. Purcell
发明人： Korbin Van Dyke , Paul Campbell , Don Van Dyke , Ali Alasti , Stephen C. Purcell
IPC分类号： G06F9/46
CPC分类号： G06F9/5044
摘要： A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using the available processing resources to produce resulting data, and the resulting data is passed to an input/output device.
摘要翻译：一种用于动态分配处理资源和任务的方法和装置，包括多媒体任务。任务排队，识别可用的处理资源，并在任务之间分配可用的处理资源。可用的处理资源具有与任务相对应的功能程序。使用可用的处理资源执行任务以产生结果数据，并将所得到的数据传递到输入/输出设备。

6. 发明授权

US06449671B1 Method and apparatus for busing data elements 失效
标题翻译：调用数据元素的方法和装置
公开(公告)号：US06449671B1
公开(公告)日：2002-09-10
申请号：US09328971
申请日：1999-06-09
申请人： Niteen A. Patkar , Stephen C. Purcell , Shalesh Thusoo , Korbin S. Van Dyke
发明人： Niteen A. Patkar , Stephen C. Purcell , Shalesh Thusoo , Korbin S. Van Dyke
IPC分类号： G06F1300
CPC分类号： G06F12/0806
摘要： A method and apparatus for busing data elements within a computing system includes processing that begins by providing, on a shared bus, a first control signal relating to a first transaction during a first bus cycle. The processing continues by providing a second control signal relating to a second transaction and a first address signal relating to the first transaction during a second bus cycle. The processing continues by providing a third control signal relating to a third transaction and a second address signal relating to a second transaction during a third bus cycle. The processing then continues by providing a first status relating to the first transaction and a third addressing signal relating to the third transaction during a fourth bus cycle. The processing then continues by providing a second status relating to the second transaction during a fifth bus cycle. The processing then continues by providing first data relating to the first transaction when the first status is a hit and providing third status relating to the third transaction during a sixth bus cycle.
摘要翻译：用于在计算系统内传送数据元素的方法和装置包括开始于在共享总线上提供在第一总线周期期间与第一事务相关的第一控制信号的处理。通过在第二总线周期期间提供与第二事务相关的第二控制信号和与第一事务相关的第一地址信号来继续处理。通过在第三总线周期期间提供与第三事务相关的第三控制信号和与第二事务相关的第二地址信号来继续处理。然后通过在第四总线周期期间提供与第一事务相关的第一状态和与第三事务相关的第三寻址信号来继续处理。然后通过在第五总线周期期间提供与第二事务相关的第二状态来继续处理。然后，当第一状态是命中时，通过提供与第一事务有关的第一数据继续处理，并在第六总线周期期间提供与第三事务有关的第三状态。

7. 发明授权

US06393453B1 Circuit and method for fast squaring 有权
标题翻译：电路和方法快速平方
公开(公告)号：US06393453B1
公开(公告)日：2002-05-21
申请号：US09159271
申请日：1998-09-22
申请人： Stephen C. Purcell
发明人： Stephen C. Purcell
IPC分类号： G06F738
CPC分类号： G06F7/552 , G06F2207/5523
摘要： A circuit for squaring an n-bit value includes a partial product bit generator which logically AND's a bit of the n-bit value having a weight 2k (k is an integer) with the same bit of weight 2k to generate a partial product bit of weight 22k. Another partial product bit generator receives and logically AND's a bit of the n-bit value of weight 2k and a bit of weight 2m (m is an integers) to generate a partial product bit of weight 2(k+m+1). The second partial product bit generator may be the only partial product bit generator in the squaring circuit to logically AND the bit of weight 2m and the bit of weight 2k. The circuit may also include other partial product bit generators. However, the required number of partial product bit generators is significantly reduced by about ½ compared to the conventional squaring circuit. The associated Wallace tree structure is simplified and made smaller because of the reduction in partial product bits. Therefore, a faster and smaller circuit for squaring is provided.
摘要翻译：用于平方n比特值的电路包括部分乘积比特发生器，逻辑上是与具有相同比特重量2k的权重为2k（k为整数）的n比特值的比特，以产生部分乘积比特体重22k。另一个部分产品位发生器接收AND逻辑AND的重量为2k的n位值的位，并且重量为2m（m为整数）的位，以产生权重为2（k + m + 1）的部分乘积位。第二部分乘积比特发生器可以是平方电路中的唯一的部分乘积比特发生器，用于逻辑上与权重2m的比特和权重2k的比特。电路还可以包括其他部分产品位发生器。然而，与常规平方电路相比，所需数量的部分产品位发生器大大减少了约1/2。由于部分产品位的减少，相关的华莱士树结构被简化并变得更小。因此，提供了更快更小的平方电路。

8. 发明授权

US6081823A Circuit and method for wrap-around sign extension for signed numbers 失效
标题翻译：用于带符号数字的环绕符号扩展的电路和方法
公开(公告)号：US6081823A
公开(公告)日：2000-06-27
申请号：US100266
申请日：1998-06-19
申请人： Stephen C. Purcell , Nital P. Patwa
发明人： Stephen C. Purcell , Nital P. Patwa
IPC分类号： G06F7/52
CPC分类号： G06F7/5338 , G06F7/49994
摘要： A multiplier has two input value terminals which receive two signed input bit groups. The multiplier also has two output terminals configured to carry a sum and carry bit group representing, in redundant form, a product of the two signed input values. A sign determining circuit generates a sign bit representing a sign of the product of the two input signed values. An extension unit has three input terminals configured to receive the most significant bit of the sum bit group, the most significant bit of the carry bit group, and the sign bit generated by the sign determining circuit. The extension unit is structure to generate a least significant extension bit and a more significant extension bit. The least significant extension bit has one binary state if the sum most significant bit, the sign bit, and the carry most significant bit have the same binary state. The least significant extension bit otherwise has the opposite binary state.
摘要翻译：乘法器具有两个输入值端子，其接收两个带符号的输入位组。乘法器还具有两个输出端子，其被配置为携带以冗余形式表示两个带符号输入值的乘积的和和携带位组。符号确定电路产生表示两个输入有符号值的积的符号的符号位。扩展单元具有三个输入端子，其被配置为接收和位组的最高有效位，进位位组的最高有效位以及由符号确定电路产生的符号位。扩展单元是生成最低有效扩展位和更重要的扩展位的结构。如果最高有效位，符号位和进位最高有效位具有相同的二进制状态，则最低有效扩展位具有一个二进制状态。最不重要的扩展位否则具有相反的二进制状态。

9. 发明授权

US5815646A Decompression processor for video applications 失效
标题翻译：解压缩处理器用于视频应用
公开(公告)号：US5815646A
公开(公告)日：1998-09-29
申请号：US296387
申请日：1994-10-11
申请人： Stephen C. Purcell , David E. Galbi , Frank H. Liao , Yvonne C. Tse
发明人： Stephen C. Purcell , David E. Galbi , Frank H. Liao , Yvonne C. Tse
IPC分类号： G06T9/00 , H03M7/42 , H04N5/44 , H04N7/26 , H04N7/30 , H04N7/50 , G06F15/16
CPC分类号： H04N19/00 , H03M7/425 , H04N19/126 , H04N19/42 , H04N19/423 , H04N19/43 , H04N19/433 , H04N19/60 , H04N19/61 , H04N19/124 , H04N19/70 , H04N5/4401
摘要： A method and structure including four video decompression structures and eight memory banks are provided for decoding high definition television (HDTV) signal. In this HDTV decompression structure, the 1920.times.1080 pixel display space is divided into four vertical sections of 480.times.1080 pixels. Each memory bank stores the values of pixels in one non-overlapping group of 240.times.1080 pixels. Each decompression structure decodes a 480.times.1088-pixel picture area with access to up to two additional 240.times.1088-pixel picture areas. The video decompression structures decode the vertical sections in lock-step to avoid the problem of the same bank of memory being accessed by more than one video decompression structure. In one embodiment of the present invention, a macroblock fetch can cross 1-4 DRAM page boundaries. So, in order to maintain the lock-step relationship of the video decompression structures, each page mode access is limited to fetching only an 8.times.8 quad pixel picture area, so that regardless of the number of DRAM page boundaries required to be crossed, four page mode access cycles are required for each reference macroblock fetched.
摘要翻译：提供包括四个视频解压缩结构和八个存储器组的方法和结构，用于解码高分辨率电视（HDTV）信号。在这个HDTV解压缩结构中，1920x1080像素的显示空间被划分为480×1080像素的四个垂直部分。每个存储体将像素的值存储在240×1080像素的一个非重叠组中。每个解压缩结构可以解码480x1088像素的图片区域，可以访问多达两个额外的240x1088像素图片区域。视频解压缩结构在锁定步骤中解码垂直部分，以避免由多个视频解压缩结构访问同一存储体的问题。在本发明的一个实施例中，宏块提取可以跨越1-4个DRAM页边界。因此，为了维持视频解压缩结构的锁步关系，每页模式访问仅限于仅获取8×8四像素图像区域，因此无论要跨越的DRAM页面边界的数量如何，四页每个参考宏块都需要模式访问周期。

10. 发明授权

US5809174A Decompression processor for video applications 失效
标题翻译：解压缩处理器用于视频应用
公开(公告)号：US5809174A
公开(公告)日：1998-09-15
申请号：US730252
申请日：1996-10-15
申请人： Stephen C. Purcell , David E. Galbi , Frank H. Liao , Yvonne C. Tse
发明人： Stephen C. Purcell , David E. Galbi , Frank H. Liao , Yvonne C. Tse
IPC分类号： G06T9/00 , H03M7/42 , H04N5/44 , H04N7/26 , H04N7/30 , H04N7/50 , H04N21/2368 , H04N21/434 , G06K9/36
CPC分类号： H04N19/00 , H03M7/425 , H04N19/126 , H04N19/42 , H04N19/423 , H04N19/43 , H04N19/433 , H04N19/61 , H04N19/124 , H04N19/60 , H04N19/70 , H04N21/42692 , H04N5/4401
摘要： A motion compensation structure and a method are provided for decoding interframe coded video data using motion vectors. The motion compensation structure includes a filter for resampling the pixel data in both vertical and horizontal directions, a prediction memory structure and a weighted adder structure. In one embodiment of the present invention, a weighted adder structure and a method are provided for performing bilinear interpolation of two values using multiplexers and an multiple-input adder.
摘要翻译：提供了一种使用运动矢量解码帧间编码视频数据的运动补偿结构和方法。运动补偿结构包括用于在垂直和水平方向上重新采样像素数据的滤波器，预测存储器结构和加权加法器结构。在本发明的一个实施例中，提供一种加权加法器结构和方法，用于使用多路复用器和多输入加法器来执行两个值的双线性插值。

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