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1. 发明授权

US5233348A Variable length code word decoder for use in digital communication systems 失效
标题翻译：用于数字通信系统的可变长度码字解码器
公开(公告)号：US5233348A
公开(公告)日：1993-08-03
申请号：US858101
申请日：1992-03-26
申请人： Stephen C. Pollmann , Paul Moroney , Edward A. Krause , Paul Shen , Woo H. Paik
发明人： Stephen C. Pollmann , Paul Moroney , Edward A. Krause , Paul Shen , Woo H. Paik
IPC分类号： H03M7/40 , G06T9/00 , H03M7/42 , H04N7/26 , H04N7/30
CPC分类号： H03M7/425 , H04N19/60 , H04N19/13 , H04N19/91
摘要： Apparatus is provided for decoding variable length code words to recover transform coefficients, such as DCT transform coefficients provided by a high definition television encoder. A first category of the code words has a length of no more than n bits. A second category has a length of greater than n bits. A feedback ROM is used to decode the code words. Code words from the first category are processed by directly addressing a lookup table in the ROM. Code words from the second category are processed using multiple passes through the ROM, wherein a portion of the data output during a prior pass is fed back to address the memory during a subsequent pass.

2. 发明授权

US5809538A DRAM arbiter for video decoder 失效
标题翻译： DRAM仲裁器用于视频解码器
公开(公告)号：US5809538A
公开(公告)日：1998-09-15
申请号：US598199
申请日：1996-02-07
申请人： Stephen C. Pollmann , Serdar Yilmaz
发明人： Stephen C. Pollmann , Serdar Yilmaz
IPC分类号： G06F13/18 , G06F12/00
CPC分类号： G06F13/18
摘要： A memory control and management system efficiently multiplexes access to a dynamic random access memory (DRAM) among several client processes in an MPEG or similar digital television delivery system or the like. These processes can include, for example, an on-screen display (OSD) graphics processor, a microprocessor interface, graphics accelerator functions, and audio and data processors. An arbiter receives packetized data from an MPEG transport layer for distribution to an associated DRAM. The arbiter sequentially time-multiplexes access to the DRAM by the client processes according to priority criteria, including the bandwidth requirements of the client processes, and whether a client process is requesting access. Access is granted for a predetermined period as long as the client is requesting access. Access can be terminated early if the client no longer requests access, or if a new row in the DRAM must be addressed, and the re-addressing period will consume the remainder of the available data transfer cycles in the access period. The invention is particularly applicable to a digital video decoder where an on-screen display graphics processor consumes a large portion of the DRAM interface bandwidth.
摘要翻译：存储器控制和管理系统在MPEG或类似的数字电视传送系统等中的多个客户端处理中高效地复用对动态随机存取存储器（DRAM）的访问。这些过程可以包括例如屏幕显示（OSD）图形处理器，微处理器接口，图形加速器功能以及音频和数据处理器。仲裁器从MPEG传输层接收分组数据以分配给相关联的DRAM。仲裁者根据优先级标准对客户端进程进行时间多路复用，包括客户端进程的带宽需求以及客户端进程是否请求访问。只要客户端请求访问，访问权限将被允许一段预定时间。如果客户端不再请求访问，或者如果DRAM中的新行必须被寻址，则访问可以提前终止，并且重新寻址周期将消耗访问周期中剩余的可用数据传输周期。本发明特别适用于数字视频解码器，其中屏幕显示图形处理器消耗DRAM接口带宽的大部分。

3. 再颁专利

USRE42225E1 System and method for timing detector measurements in a wireless communication system 有权
标题翻译：用于在无线通信系统中定时检测器测量的系统和方法
公开(公告)号：USRE42225E1
公开(公告)日：2011-03-15
申请号：US11429637
申请日：2006-05-04
申请人： Kenneth L. Stanwood , Moti Kabelly , Jacques Behar , Yossi Keren , Stephen C. Pollmann , David Gazelle
发明人： Kenneth L. Stanwood , Moti Kabelly , Jacques Behar , Yossi Keren , Stephen C. Pollmann , David Gazelle
IPC分类号： H04W88/00 , H04W4/00 , H04M1/00
CPC分类号： H04W84/14
摘要： A system that provides a wireless broadband connection between base stations and customer sites is described. The system includes indoor units within the base stations and customer sites and communicate across cables to outdoor units. The indoor units link to routers, switches and other devices and services. The outdoor units transmit and receive wireless data and send it to the indoor units. The indoor units control the timing of detector measurements in the outdoor unit by transmitting a regular, repeating control message at a predetermined time. Once the outdoor unit receives the control message, it samples its detectors and reports measurements back to the indoor unit.
摘要翻译：描述了在基站和客户站点之间提供无线宽带连接的系统。该系统包括基站和客户站点内的室内单元，并通过电缆与户外单元进行通信。室内单元链接到路由器，交换机和其他设备和服务。室外机发送和接收无线数据并发送到室内机。室内单元通过在预定时间发送常规重复的控制消息来控制室外单元中的检测器测量的定时。一旦室外机接收到控制信息，就会对其检测器进行采样并将测量结果报告给室内机。

4. 再颁专利

USRE42021E1 Equalizer performance enhancements for broadband wireless applications 有权
标题翻译：宽带无线应用的均衡器性能增强
公开(公告)号：USRE42021E1
公开(公告)日：2011-01-04
申请号：US11187034
申请日：2005-07-20
申请人： Stephen C. Pollmann , Eli Arviv , Jacques Behar , Timothy L. Gallagher , David Gazelle , Frederick W. Price
发明人： Stephen C. Pollmann , Eli Arviv , Jacques Behar , Timothy L. Gallagher , David Gazelle , Frederick W. Price
IPC分类号： H04B1/38 , H03H7/30 , H03K5/159
CPC分类号： H04L1/20 , H04L1/0003 , H04L1/0036 , H04L1/004 , H04L7/0029 , H04L7/042 , H04L25/03057 , H04L27/0012 , H04L27/3809 , H04L2025/03401 , H04L2025/0342 , H04L2025/03668 , H04L2025/03783
摘要： A system and method for enhancing the performance of an equalizer in a modem. Multiple techniques are disclosed which improve the modem performance. A first technique uses stored parameters for each burst from each remote site to demodulate a received data stream. A second technique compensates for the gain droop caused by storing parameters across each burst. A third technique minimizes errors caused by adapting the equalizer coefficients for each data burst by analyzing the SN ratio and error rate of the received burst. A fourth technique improves the convergence of the equalizer by using a two-part preamble, whereby both parts are transmitted using different modulation techniques. A fifth technique is provided which performs a soft reset of the modem without performing a complete reset of the modem. A sixth technique determines a modem adaptation factor based on the expected modulation type of an incoming burst transmission. A seventh technique calculates a phase correction value for the stored tap values and applies the value to the incoming signal.
摘要翻译：一种用于增强调制解调器中的均衡器的性能的系统和方法。公开了改进调制解调器性能的多种技术。第一种技术使用来自每个远程站点的每个突发的存储参数来解调所接收的数据流。第二种技术补偿了通过在每个突发之间存储参数而引起的增益下降。第三种技术通过分析接收到的突发的SN比和错误率来最小化通过针对每个数据突发调整均衡器系数而引起的误差。第四种技术通过使用两部分前导码来改善均衡器的收敛，由此两部分都使用不同的调制技术进行发送。提供了在不执行调制解调器的完全复位的情况下执行调制解调器的软复位的第五种技术。第六种技术基于输入突发传输的预期调制类型来确定调制解调器适配因子。第七种技术计算存储的抽头值的相位校正值，并将该值应用于输入信号。

5. 发明授权

US06944188B2 Synchronizing clocks across a communication link 失效
标题翻译：通过通信链路同步时钟
公开(公告)号：US06944188B2
公开(公告)日：2005-09-13
申请号：US09790443
申请日：2001-02-21
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Ell Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Ell Arviv
IPC分类号： H04J3/06 , H04L7/04 , H04L7/08 , H04L12/56 , G06F15/16 , H04B1/38 , H04L12/28 , H04Q7/00
CPC分类号： H04J3/0658 , H04L7/042 , H04L7/08 , H04W48/08 , H04W56/00 , H04W84/20
摘要： Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.
摘要翻译：用于在通信链路上同步一个或多个时钟的装置，系统和方法。从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。同步信号可以是以从机侧预期的间隔发送的预期信号模式。从时钟可以将接收的信号与预期同步信号的表示相关，以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。通过相关采样序列指示的同步信号接收时间可以通过围绕最佳相关样本内插相关采样序列来精细化，以便以小于样本分辨率的插值分辨率来定位最佳内插。可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较，该从时钟被调整直到时间匹配。在初始化之后，优选地累积所有从时钟错误以防止从机和主时钟之间的长期滑动。通过通信链路同步的以前独立的主，从时钟构成了一个非常见的时钟，可以在链路的每一侧与次级独立时钟进行比较，然后可以通过调整二次独立时钟来与其独立时钟相同的差异本地非通用时钟作为链路另一侧的辅助时钟源自其本地非通用时钟。

6. 发明授权

US08199779B2 Synchronizing clocks across a communication link 有权
标题翻译：通过通信链路同步时钟
公开(公告)号：US08199779B2
公开(公告)日：2012-06-12
申请号：US13021627
申请日：2011-02-04
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
IPC分类号： H04J3/16 , G06F15/16 , H04B1/38
CPC分类号： H04J3/0658 , H04L7/042 , H04L7/08 , H04W48/08 , H04W56/00 , H04W84/20
摘要： Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.
摘要翻译：用于在通信链路上同步一个或多个时钟的装置，系统和方法。从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。同步信号可以是以从机侧预期的间隔发送的预期信号模式。从时钟可以将接收的信号与预期同步信号的表示相关，以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。通过相关采样序列指示的同步信号接收时间可以通过围绕最佳相关样本内插相关采样序列来精细化，以便以小于样本分辨率的插值分辨率定位最佳内插。可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较，该从时钟被调整直到时间匹配。在初始化之后，优选地累积所有从时钟错误以防止从机和主时钟之间的长期滑动。通过通信链路同步的以前独立的主，从时钟构成了一个非常见的时钟，可以在链路的每一侧与次级独立时钟进行比较，然后可以通过调整二次独立时钟来与其独立时钟相同的差异本地非通用时钟作为链路另一侧的辅助时钟源自其本地非通用时钟。

7. 发明授权

US07583705B2 Synchronizing clocks across a communication link 失效
标题翻译：通过通信链路同步时钟
公开(公告)号：US07583705B2
公开(公告)日：2009-09-01
申请号：US11170391
申请日：2005-06-29
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
IPC分类号： H04J3/06 , H04B1/38 , H04W4/00
CPC分类号： H04J3/0658 , H04L7/042 , H04L7/08 , H04W48/08 , H04W56/00 , H04W84/20
摘要： One or more clocks are synchronized across a communication link using a synchronization signal sent from a master to a slave clock. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate. The synchronization signal receipt time is compared to the expected time and the slave clock is adjusted until the times match. Master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks. The secondary independent clocks may be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.
摘要翻译：使用从主机发送到从时钟的同步信号，通过通信链路同步一个或多个时钟。同步信号可以是以从站所预期的间隔发送的预期信号模式。从时钟可以将接收的信号与预期同步信号的表示相关，以产生第一采样率的相关采样序列。将同步信号接收时间与预期时间进行比较，并调整从时钟直到时间匹配。通过通信链路同步的主和从时钟构成了一个非常见的时钟，可以在链路的每一侧与次级独立时钟进行比较。辅助独立时钟可以通过调整一个来独立同步，以使其与本地非常见时钟具有相同的差异，因为链路另一侧的辅助时钟与其本地非常见时钟相同。

8. 发明授权

US06597733B2 Equalizer performance enhancements for broadband wireless applications 有权
公开(公告)号：US06597733B2
公开(公告)日：2003-07-22
申请号：US09800268
申请日：2001-03-05
申请人： Stephen C. Pollmann , Eli Arviv , Jacques Behar , Timothy L. Gallagher , David Gazelle , Frederick W. Price
发明人： Stephen C. Pollmann , Eli Arviv , Jacques Behar , Timothy L. Gallagher , David Gazelle , Frederick W. Price
IPC分类号： H04B138
CPC分类号： H04L1/20 , H04L1/0003 , H04L1/0036 , H04L1/004 , H04L7/0029 , H04L7/042 , H04L25/03057 , H04L27/0012 , H04L27/3809 , H04L2025/03401 , H04L2025/0342 , H04L2025/03668 , H04L2025/03783
摘要： A system and method for enhancing the performance of an equalizer in a modem. Multiple techniques are disclosed which improve the modem performance. A first technique uses stored parameters for each burst from each remote site to demodulate a received data stream. A second technique compensates for the gain droop caused by storing parameters across each burst. A third technique minimizes errors caused by adapting the equalizer coefficients for each data burst by analyzing the SN ratio and error rate of the received burst. A fourth technique improves the convergence of the equalizer by using a two-part preamble, whereby both parts are transmitted using different modulation techniques. A fifth technique is provided which performs a soft reset of the modem without performing a complete reset of the modem. A sixth technique determines a modem adaptation factor based on the expected modulation type of an incoming burst transmission. A seventh technique calculates a phase correction value for the stored tap values and applies the value to the incoming signal.

9. 发明申请

US20110122981A1 SYNCHRONIZING CLOCKS ACROSS A COMMUNICATION LINK 有权
标题翻译：通信链路同步时钟
公开(公告)号：US20110122981A1
公开(公告)日：2011-05-26
申请号：US13021627
申请日：2011-02-04
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
IPC分类号： H04L7/00
CPC分类号： H04J3/0658 , H04L7/042 , H04L7/08 , H04W48/08 , H04W56/00 , H04W84/20
摘要： Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.
摘要翻译：用于在通信链路上同步一个或多个时钟的装置，系统和方法。从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。同步信号可以是以从机侧预期的间隔发送的预期信号模式。从时钟可以将接收的信号与预期同步信号的表示相关，以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。通过相关采样序列指示的同步信号接收时间可以通过围绕最佳相关样本内插相关采样序列来精细化，以便以小于样本分辨率的插值分辨率定位最佳内插。可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较，该从时钟被调整直到时间匹配。在初始化之后，优选地累积所有从时钟错误以防止从机和主时钟之间的长期滑动。通过通信链路同步的以前独立的主，从时钟构成了一个非常见的时钟，可以在链路的每一侧与次级独立时钟进行比较，然后可以通过调整二次独立时钟来与其独立时钟相同的差异本地非通用时钟作为链路另一侧的辅助时钟源自其本地非通用时钟。

10. 发明授权

US07907640B2 Synchronizing clocks across a communication link 有权
标题翻译：通过通信链路同步时钟
公开(公告)号：US07907640B2
公开(公告)日：2011-03-15
申请号：US12508431
申请日：2009-07-23
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
IPC分类号： H04J3/16 , H04J3/06 , H04L7/00
CPC分类号： H04J3/0658 , H04L7/042 , H04L7/08 , H04W48/08 , H04W56/00 , H04W84/20
摘要： A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. A best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output.
摘要翻译：从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。同步信号可以是以从机侧预期的间隔发送的预期信号模式。从时钟可以将接收的信号与预期同步信号的表示相关，以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较，该从时钟被调整直到时间匹配。可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。

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