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1. 发明授权

US07779239B2 User opt-in processor feature control capability 有权
标题翻译：用户选择加入处理器功能控制功能
公开(公告)号：US07779239B2
公开(公告)日：2010-08-17
申请号：US10900875
申请日：2004-07-28
申请人： Stephen A. Fischer , Dion Rodgers , James A. Sutton
发明人： Stephen A. Fischer , Dion Rodgers , James A. Sutton
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/30101 , G06F9/30181 , G06F21/629
摘要： A processor includes a feature control unit to enable or disable one or more processor features individually in response to a user selectable setting. The feature control unit is adapted to disable the processor feature(s) if the user setting has not been updated in accordance with an input regardless of the value of the user setting prior to the update and to enable or disable the processor feature(s) in accordance with the updated user setting after it has been updated. The feature control unit may also include a lock unit to prevent changes to the updated user setting and a software feature selection unit to enable or disable processor features in response to a software feature selection setting and, optionally, only enable or disable processor features whose corresponding updated user setting is user enabled. The feature control unit may also include mechanisms to detect illegal feature selection conditions.
摘要翻译：处理器包括特征控制单元，以响应于用户可选择的设置来单独启用或禁用一个或多个处理器特征。如果没有根据输入更新用户设置而不考虑更新之前的用户设置的值，并且启用或禁用处理器特征，则特征控制单元适于禁用处理器特征，根据更新后的用户设置进行更新。特征控制单元还可以包括用于防止更新的用户设置的改变的锁定单元和软件特征选择单元以响应于软件特征选择设置来启用或禁用处理器特征，并且可选地，仅启用或禁用其相应的处理器特征更新的用户设置是用户启用的。特征控制单元还可以包括检测非法特征选择条件的机制。

2. 发明申请

US20060026525A1 User opt-in processor feature control capability 有权
标题翻译：用户选择加入处理器功能控制功能
公开(公告)号：US20060026525A1
公开(公告)日：2006-02-02
申请号：US10900875
申请日：2004-07-28
申请人： Stephen A. Fischer , Dion Rodgers , James Sutton
发明人： Stephen A. Fischer , Dion Rodgers , James Sutton
IPC分类号： G06F17/00
CPC分类号： G06F9/30101 , G06F9/30181 , G06F21/629
摘要： A processor includes a feature control unit to enable or disable one or more processor features individually in response to a user selectable setting. The feature control unit is adapted to disable the processor feature(s) if the user setting has not been updated in accordance with an input regardless of the value of the user setting prior to the update and to enable or disable the processor feature(s) in accordance with the updated user setting after it has been updated. The feature control unit may also include a lock unit to prevent changes to the updated user setting and a software feature selection unit to enable or disable processor features in response to a software feature selection setting and, optionally, only enable or disable processor features whose corresponding updated user setting is user enabled. The feature control unit may also include mechanisms to detect illegal feature selection conditions.
摘要翻译：处理器包括特征控制单元，以响应于用户可选择的设置来单独启用或禁用一个或多个处理器特征。如果没有根据输入更新用户设置而不考虑更新之前的用户设置的值，并且启用或禁用处理器特征，则特征控制单元适于禁用处理器特征，根据更新后的用户设置进行更新。特征控制单元还可以包括用于防止更新的用户设置的改变的锁定单元和软件特征选择单元以响应于软件特征选择设置来启用或禁用处理器特征，并且可选地，仅启用或禁用其相应的处理器特征更新的用户设置是用户启用的。特征控制单元还可以包括检测非法特征选择条件的机制。

3. 发明申请

US20130042093A1 CONTEXT STATE MANAGEMENT FOR PROCESSOR FEATURE SETS 有权
标题翻译：处理器特征集的上下文状态管理
公开(公告)号：US20130042093A1
公开(公告)日：2013-02-14
申请号：US11967303
申请日：2007-12-31
申请人： Don A. Van Dyke , Michael Mishaeli , Ittai Anati , Baiju V. Patel , Will Deutsch , Rajesh Shah , Gilbert Neiger , James B. Crossland , Chris J. Newburn , Bryant E. Bigbee , Muhammad Faisal Azeem , John L. Reid , Dion Rodgers
发明人： Don A. Van Dyke , Michael Mishaeli , Ittai Anati , Baiju V. Patel , Will Deutsch , Rajesh Shah , Gilbert Neiger , James B. Crossland , Chris J. Newburn , Bryant E. Bigbee , Muhammad Faisal Azeem , John L. Reid , Dion Rodgers
IPC分类号： G06F9/312
CPC分类号： G06F9/30043 , G06F9/30003 , G06F9/30101 , G06F9/461
摘要： Embodiments of an invention related to context state management based on processor features are disclosed. In one embodiment, a processor includes instruction logic and state management logic. The instruction logic is to receive a state management instruction having a parameter to identify a subset of the features supported by the processor. The state management logic is to perform a state management operation specified by the state management instruction.
摘要翻译：公开了与基于处理器特征的上下文状态管理相关的发明的实施例。在一个实施例中，处理器包括指令逻辑和状态管理逻辑。指令逻辑是接收具有参数的状态管理指令，以识别由处理器支持的特征的子集。状态管理逻辑是执行由状态管理指令指定的状态管理操作。

4. 发明申请

US20130031557A1 System To Profile And Optimize User Software In A Managed Run-Time Environment 有权
标题翻译：在管理运行时环境中配置和优化用户软件的系统
公开(公告)号：US20130031557A1
公开(公告)日：2013-01-31
申请号：US13529630
申请日：2012-06-21
申请人： Chris J. Newburn , Robert Knight , Robert Geva , Dion Rodgers , Xiang Zou , Hong Wang , Bryant E. Bigbee , Ittai Anati
发明人： Chris J. Newburn , Robert Knight , Robert Geva , Dion Rodgers , Xiang Zou , Hong Wang , Bryant E. Bigbee , Ittai Anati
IPC分类号： G06F9/46
CPC分类号： G06F9/542 , G06F11/348 , G06F11/3612 , G06F2201/86 , G06F2201/885
摘要： Method, apparatus, and system for monitoring performance within a processing resource, which may be used to modify user-level software. Some embodiments of the invention pertain to an architecture to allow a user to improve software running on a processing resources on a per-thread basis in real-time and without incurring significant processing overhead.
摘要翻译：用于监控处理资源内的性能的方法，装置和系统，其可用于修改用户级软件。本发明的一些实施例涉及允许用户实时地在每个线程的基础上改进在处理资源上运行的软件并且不产生显着的处理开销的架构。

5. 发明申请

US20130024861A1 Virtualization Event Processing in a Layered Virtualization Architecuture 审中-公开
标题翻译：分层虚拟化架构中的虚拟化事件处理
公开(公告)号：US20130024861A1
公开(公告)日：2013-01-24
申请号：US13595838
申请日：2012-08-27
申请人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Dion Rodgers , Richard A. Uhlig , Lawrence O. Smith , Barry E. Huntley
发明人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Dion Rodgers , Richard A. Uhlig , Lawrence O. Smith , Barry E. Huntley
IPC分类号： G06F9/455
CPC分类号： G06F9/45533 , G06F9/3861 , G06F9/45545 , G06F9/4555 , G06F9/45558 , G06F9/4812 , G06F9/542 , G06F13/24 , G06F2009/45566
摘要： Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.
摘要翻译：公开了在分层虚拟化架构中处理虚拟化事件的装置和方法的实施例。在一个实施例中，装置包括事件逻辑和评估逻辑。事件逻辑是识别虚拟化事件。评估逻辑是为了响应于虚拟化事件来确定是否将控制从子客户端传送到父访客。

6. 发明授权

US08291410B2 Controlling virtual machines based on activity state 有权
标题翻译：基于活动状态控制虚拟机
公开(公告)号：US08291410B2
公开(公告)日：2012-10-16
申请号：US11618440
申请日：2006-12-29
申请人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Dion Rodgers , Barry E. Huntley , Lawrence O. Smith , Shashank Shekhar
发明人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Dion Rodgers , Barry E. Huntley , Lawrence O. Smith , Shashank Shekhar
IPC分类号： G06F9/455
CPC分类号： G06F9/45558 , G06F2009/45566
摘要： Embodiments of apparatuses, methods, and systems for controlling virtual machines based on activity state are disclosed. In one embodiment, an apparatus includes virtual machine entry logic and activity state evaluation logic. The virtual machine entry logic is to transfer control of the apparatus from a host to a guest. The activity state evaluation logic is to determine whether the activity state of the guest would be inactive upon receiving control.
摘要翻译：公开了用于基于活动状态来控制虚拟机的设备，方法和系统的实施例。在一个实施例中，装置包括虚拟机入口逻辑和活动状态评估逻辑。虚拟机入口逻辑是将设备的控制从主机传送到访客。活动状态评估逻辑是确定访客的活动状态是否在接收到控制时处于不活动状态。

7. 发明申请

US20120110299A1 SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE 有权
标题翻译：与扩展的寻呼表同步一个翻译书签缓冲区
公开(公告)号：US20120110299A1
公开(公告)日：2012-05-03
申请号：US13348608
申请日：2012-01-11
申请人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Dion Rodgers , Rajesh Madukkaraumukumana , Camron Rust , Sebastian Schoenberg
发明人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Dion Rodgers , Rajesh Madukkaraumukumana , Camron Rust , Sebastian Schoenberg
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
摘要： A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
摘要翻译：一种处理器，包括执行指令以使来自基于虚拟化的系统的客户机的物理地址（客户物理地址）到基于虚拟化系统的主机的物理地址（主机物理地址）的映射同步的指令，并且存储在翻译后备缓冲器（TLB），其中相应的映射存储在基于虚拟化的系统的扩展分页表（EPT）中。

8. 发明申请

US20070005870A1 Virtualizing memory type 有权
标题翻译：虚拟化内存类型
公开(公告)号：US20070005870A1
公开(公告)日：2007-01-04
申请号：US11171993
申请日：2005-06-29
申请人： Gilbert Neiger , Steven Bennett , Andrew Anderson , Dion Rodgers , David Koufaty , Richard Uhlig , Camron Rust , Larry Smith , Rupin Vakharwala
发明人： Gilbert Neiger , Steven Bennett , Andrew Anderson , Dion Rodgers , David Koufaty , Richard Uhlig , Camron Rust , Larry Smith , Rupin Vakharwala
IPC分类号： G06F21/00
CPC分类号： G06F12/1009 , G06F9/45537
摘要： A processor, capable of operation in a host machine, including memory management logic to support a plurality of memory types for a physical memory access by the processor, and virtualization support logic to determine a host memory type for a reference to a memory location by a guest in a virtual machine executable on the processor based at least in part on a memory type field stored in an entry of an extended paging table of a virtualization support system of the host machine (extended memory type field), to determine a guest memory type for the reference to the memory location, and to determine an effective memory type based on at least one of the host memory type and the guest memory type.
摘要翻译：能够在主机中操作的处理器，包括用于支持由处理器进行物理存储器访问的多种存储器类型的存储器管理逻辑，以及虚拟化支持逻辑，以通过以下方式来确定用于引用存储器位置的主机存储器类型至少部分地基于存储在主机的虚拟化支持系统（扩展存储器类型字段）的扩展寻呼表的条目中的存储器类型字段来在处理器上执行的虚拟机中的客户端，以确定客户机存储器类型用于引用存储器位置，并且基于主机存储器类型和来宾存储器类型中的至少一个来确定有效的存储器类型。

9. 发明申请

US20060161719A1 Virtualizing physical memory in a virtual machine system 有权
标题翻译：虚拟化虚拟机系统中的物理内存
公开(公告)号：US20060161719A1
公开(公告)日：2006-07-20
申请号：US11036736
申请日：2005-01-14
申请人： Steven Bennett , Andrew Anderson , Gilbert Neiger , Rajesh Madukkarumukumana , Richard Uhlig , Larry Smith , Dion Rodgers
发明人： Steven Bennett , Andrew Anderson , Gilbert Neiger , Rajesh Madukkarumukumana , Richard Uhlig , Larry Smith , Dion Rodgers
IPC分类号： G06F21/00
CPC分类号： G06F12/1483 , G06F9/45533 , G06F9/45558 , G06F12/109 , G06F2009/45583 , G06F2212/151 , G06F2212/152 , G06F2212/657
摘要： A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.
摘要翻译：一种处理器，其包括具有存储器虚拟化支持系统的处理器的虚拟化系统，以将参考映射到由虚拟机上可执行的客户机软件制成的客体物理存储器，该虚拟机器又可在主机上执行，其中处理器可操作为引用主机的主机物理内存。

10. 发明授权

US06357016B1 Method and apparatus for disabling a clock signal within a multithreaded processor 有权
公开(公告)号：US06357016B1
公开(公告)日：2002-03-12
申请号：US09458589
申请日：1999-12-09
申请人： Dion Rodgers , Bret Toll , Aimee Wood
发明人： Dion Rodgers , Bret Toll , Aimee Wood
IPC分类号： G06F108
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F9/384 , G06F9/3851 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： A method includes maintaining an indication of a pending event with respect to each of a number of threads supported within a multithreaded processor. An indication is also maintained of an active or inactive state for each of the multiple threads. A clock disable condition is detected. This clock disable condition may be indicated by the absence of pending events with respect to each of the multiple threads and an inactive state for each of the multiple threads. A clocks signal, if enabled, is then disabled with respect to at least one functional unit within the multithreaded processor responsive to the detection of the clock disable condition.

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