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1. 发明申请

US20090204413A1 METHOD AND SYSTEM FOR ASYMMETRIC INDEPENDENT AUDIO RENDERING 有权
标题翻译：不对称独立音频渲染的方法和系统
公开(公告)号：US20090204413A1
公开(公告)日：2009-08-13
申请号：US12342327
申请日：2008-12-23
申请人： Stephane Sintes , Franck Seigneret , Christophe Favergeon-Borgialli
发明人： Stephane Sintes , Franck Seigneret , Christophe Favergeon-Borgialli
IPC分类号： G10L19/00
CPC分类号： G10L19/16
摘要： Methods and mobile devices are provided for asymmetric independent processing of audio streams in a system on a chip (SOC). More specifically, independent audio paths are provided for processors performing audio processing on the SOC and mixing of decoded audio samples from the processors is performed digitally on the SOC by a hardware digital mixer.
摘要翻译：提供了用于片上系统（SOC）中的音频流的非对称独立处理的方法和移动设备。更具体地，针对对SOC执行音频处理的处理器提供独立音频路径，并且通过硬件数字混频器在SOC上数字地执行来自处理器的解码音频样本的混合。

2. 发明授权

US08200479B2 Method and system for asymmetric independent audio rendering 有权
标题翻译：非对称独立音频渲染方法与系统
公开(公告)号：US08200479B2
公开(公告)日：2012-06-12
申请号：US12342327
申请日：2008-12-23
申请人： Stephane Sintes , Franck Seigneret , Christophe Favergeon-Borgialli
发明人： Stephane Sintes , Franck Seigneret , Christophe Favergeon-Borgialli
IPC分类号： G10L19/00 , G10L21/00 , G10L11/00 , G10L19/14
CPC分类号： G10L19/16
摘要： Methods and mobile devices are provided for asymmetric independent processing of audio streams in a system on a chip (SOC). More specifically, independent audio paths are provided for processors performing audio processing on the SOC and mixing of decoded audio samples from the processors is performed digitally on the SOC by a hardware digital mixer.
摘要翻译：提供了用于片上系统（SOC）中的音频流的非对称独立处理的方法和移动设备。更具体地，针对对SOC执行音频处理的处理器提供独立音频路径，并且通过硬件数字混频器在SOC上数字地执行来自处理器的解码音频样本的混合。

3. 发明授权

US07809961B2 Standby mode for power management 有权
标题翻译：待机模式进行电源管理
公开(公告)号：US07809961B2
公开(公告)日：2010-10-05
申请号：US11559388
申请日：2006-11-13
申请人： Franck Dahan , Franck Seigneret , Gilles Dubost
发明人： Franck Dahan , Franck Seigneret , Gilles Dubost
IPC分类号： G06F1/00 , G06F3/038 , H04B7/185 , H04B1/04 , H04B1/16 , H04B7/00 , H04B1/38 , G09G3/18 , G11C5/14
CPC分类号： G06F1/3237 , G06F1/3228 , Y02D10/128 , Y02D50/20
摘要： An apparatus and method for controlling standby mode in an electronic device. In standby mode, power and clock signals are reduced or stopped to conserve power. The apparatus includes an initiator module coupled to a power and clock control module (PCCM). When the initiator module meets conditions for standby mode, the initiator module sends a standby signal to the PCCM and does not interact with other initiator, target, or interconnect modules. When the PCCM communicates a wait signal, the initiator module enters standby mode. When the initiator module detects a wakeup event, the standby signal is deactivated. In this state, the initiator module may process information but may not interact with other modules. When the PCCM deactivates the wait signal and returns power and clock signal to steady state levels, initiator module may resume normal operation.
摘要翻译：一种用于控制电子设备中的待机模式的装置和方法。在待机模式下，电源和时钟信号被减少或停止以节省电力。该装置包括耦合到电源和时钟控制模块（PCCM）的启动器模块。当启动器模块满足待机模式条件时，启动器模块向PCCM发送备用信号，不与其他启动器，目标或互连模块进行交互。当PCCM通信等待信号时，启动器模块进入待机模式。当启动器模块检测到唤醒事件时，待机信号被禁用。在这种状态下，启动器模块可以处理信息，但是可能不与其他模块进行交互。当PCCM关闭等待信号并将电源和时钟信号恢复到稳定状态时，启动器模块可以恢复正常工作。

4. 发明授权

US07737986B2 Methods and systems for tiling video or still image data 有权
标题翻译：用于平铺视频或静态图像数据的方法和系统
公开(公告)号：US07737986B2
公开(公告)日：2010-06-15
申请号：US11617820
申请日：2006-12-29
申请人： Franck Seigneret , Sylvain Dubois , Jean Pierre Noel , Pierre-Yves J. Taloud
发明人： Franck Seigneret , Sylvain Dubois , Jean Pierre Noel , Pierre-Yves J. Taloud
IPC分类号： G06F12/10 , G06F12/00 , G06F9/26 , G06F9/34 , G06G5/399
CPC分类号： G09G5/39 , G09G2360/122
摘要： The present disclosure describes methods and systems for tiling video or still image data. At least some preferred embodiments include a method for accessing data that includes partitioning a display of graphical data into a plurality of two-dimensional tiles; mapping a two-dimensional tile of the plurality of two-dimensional tiles to a single memory row within a memory; and maintaining the graphical data for the two-dimensional tile in the single memory row.
摘要翻译：本公开描述了用于平铺视频或静止图像数据的方法和系统。至少一些优选实施例包括用于访问数据的方法，包括将图形数据的显示分割成多个二维瓦片; 将所述多个二维瓦片中的二维瓦片映射到存储器内的单个存储器行; 并且在单个存储器行中维护二维瓦片的图形数据。

5. 发明申请

US20080055325A1 METHODS AND SYSTEMS FOR TILING VIDEO OR STILL IMAGE DATA 有权
标题翻译：用于倾斜视频或静止图像数据的方法和系统
公开(公告)号：US20080055325A1
公开(公告)日：2008-03-06
申请号：US11617820
申请日：2006-12-29
申请人： Franck Seigneret , Sylvain Dubois , Jean Pierre Noel , Pierre-Yves J. Taloud
发明人： Franck Seigneret , Sylvain Dubois , Jean Pierre Noel , Pierre-Yves J. Taloud
IPC分类号： G06F13/00 , G09G5/39
CPC分类号： G09G5/39 , G09G2360/122
摘要： The present disclosure describes methods and systems for tiling video or still image data. At least some preferred embodiments include a method for accessing data that includes partitioning a display of graphical data into a plurality of two-dimensional tiles; mapping a two-dimensional tile of the plurality of two-dimensional tiles to a single memory row within a memory; and maintaining the graphical data for the two-dimensional tile in the single memory row.
摘要翻译：本公开描述了用于平铺视频或静止图像数据的方法和系统。至少一些优选实施例包括用于访问数据的方法，包括将图形数据的显示分割成多个二维瓦片; 将所述多个二维瓦片中的二维瓦片映射到存储器内的单个存储器行; 并且在单个存储器行中维护二维瓦片的图形数据。

6. 发明授权

US06970207B1 Anti-flicker filtering process and system 有权
标题翻译：防闪烁过滤和系统
公开(公告)号：US06970207B1
公开(公告)日：2005-11-29
申请号：US09644957
申请日：2000-08-23
申请人： Franck Seigneret , Philippe Monnier , Emmanuel Chiaruzzi
发明人： Franck Seigneret , Philippe Monnier , Emmanuel Chiaruzzi
IPC分类号： H04N5/44 , H04N5/21
CPC分类号： H04N7/0132
摘要： A process of filtering digital images to reduce image flicker. An anti-flicker filtering is performed after a step of calculating the image and before a step of displaying the image so that the flicker is filtered as soon as the image is created.
摘要翻译：过滤数字图像以减少图像闪烁的过程。在计算图像的步骤之后和在显示图像的步骤之前执行防闪烁滤波，使得一旦创建图像，则闪烁被滤波。

7. 发明授权

US07761617B2 Multi-threaded DMA 有权
标题翻译：多线程DMA
公开(公告)号：US07761617B2
公开(公告)日：2010-07-20
申请号：US11082564
申请日：2005-03-17
申请人： Franck Seigneret , Sivayya Ayinala , Nabil Khalifa , Praveen Kolli , Prabha Atluri
发明人： Franck Seigneret , Sivayya Ayinala , Nabil Khalifa , Praveen Kolli , Prabha Atluri
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes two decoupled read and write contexts and schedulers (302, 304) that provide for more efficient buffering and pipelining. The schedulers (302, 304) are mainly arbitrating between channels at a thread boundary. One thread is associated to one DMA service where a service can be a single or burst transaction. The multithreaded DMA transfer allows for concurrent channel transfers.
摘要翻译：直接存储器访问（DMA）电路（200）包括读取端口（202）和写入端口（204）。 DMA电路（200）是具有在读端口（202）上的“m”个线程和写入端口（204）上的“n”个线程的多线程启动器。 DMA电路（200）包括提供更有效的缓冲和流水线化的两个解耦的读和写上下文和调度器（302,304）。调度器（302,304）主要在线程边界处的信道之间进行仲裁。一个线程与一个DMA服务相关联，其中服务可以是单个或突发事务。多线程DMA传输允许并发通道传输。

8. 发明授权

US07373437B2 Multi-channel DMA with shared FIFO 有权
标题翻译：具有共享FIFO的多通道DMA
公开(公告)号：US07373437B2
公开(公告)日：2008-05-13
申请号：US11080277
申请日：2005-03-15
申请人： Franck Seigneret , Nabil Khalifa , Sivayya Ayinala , Praveen Kolli
发明人： Franck Seigneret , Nabil Khalifa , Sivayya Ayinala , Praveen Kolli
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes a data FIFO (210) which is shared by all of the logical channels and the FIFO depth can be allocated dynamically allowing for the maximum number of channels to be scheduled and concurrently active. The FIFO (210) can also be allocated to a single channel if there is only one logical channel active. The FIFO (210) increases the DMA's transfer performance, pre-fetch capacity and buffering, while maximizing pipelining.
摘要翻译：直接存储器访问（DMA）电路（200）包括读取端口（202）和写入端口（204）。 DMA电路（200）是具有在读端口（202）上的“m”个线程和写入端口（204）上的“n”个线程的多线程启动器。 DMA电路（200）包括由所有逻辑信道共享的数据FIFO（210），并且可以动态地分配FIFO深度，允许调度和同时激活最大数量的信道。如果只有一个逻辑信道有效，则FIFO（210）也可以被分配给单个信道。 FIFO（210）增加DMA的传输性能，预取容量和缓冲，同时最大化流水线。

9. 发明申请

US20070279432A1 Method and Apparatus for Spatial and Temporal Dithering 有权
标题翻译：空间和时间抖动的方法和装置
公开(公告)号：US20070279432A1
公开(公告)日：2007-12-06
申请号：US11611299
申请日：2006-12-15
申请人： Jean Noel , Franck Seigneret
发明人： Jean Noel , Franck Seigneret
IPC分类号： G09G5/02
CPC分类号： G09G5/02 , G09G3/2055
摘要： An apparatus and method for spatially and temporally dithering pixels. A pixel comprising at least one color component of a first size is provided. A dither addend is determined based on the display position of the pixel. The dither addend is added to the color component, and the color component is rounded to a second size. In one embodiment, a first frame may be provided for displaying the first pixel, the dither addend corresponding to the first frame. One or more additional frames for displaying the first pixel are provided, and one or more additional dither addends corresponding to the first pixel in the additional frames may be determined. The dither addend is different from the additional dither addends, and the additional dither addends are different from each other.
摘要翻译：用于空间和时间抖动像素的装置和方法。提供包括至少一个第一尺寸的颜色分量的像素。基于像素的显示位置来确定抖动加数。将抖动加数添加到颜色分量，并将颜色分量四舍五入为第二大小。在一个实施例中，可以提供第一帧以显示第一像素，对应于第一帧的抖动加数。提供用于显示第一像素的一个或多个附加帧，并且可以确定与附加帧中的第一像素对应的一个或多个附加抖动加数。抖动加数与附加抖动加数不同，并且附加抖动加数彼此不同。

10. 发明授权

US06788348B1 Method and system for processing digital images 有权
标题翻译：数字图像处理方法及系统
公开(公告)号：US06788348B1
公开(公告)日：2004-09-07
申请号：US09718076
申请日：2000-11-21
申请人： Emmanuel Chiaruzzi , Franck Seigneret
发明人： Emmanuel Chiaruzzi , Franck Seigneret
IPC分类号： H04N701
CPC分类号： H04N11/20 , H04N9/641
摘要： Transforming digital images including luminance data relating to points with first coordinates and chrominance data relating to points with second coordinates is performed. More particularly, the transforming is performed where one of the luminance data and the chrominance data is more numerous than the other. This is done by processing the least numerous data by filtering to obtain least numerous data relating to points with identical coordinates to those of the most numerous data.
摘要翻译：执行包括与具有第一坐标的点相关的亮度数据和与具有第二坐标的点有关的色度数据的数字图像的变换。更具体地，在亮度数据和色度数据之一比另一个更多的情况下执行变换。这是通过过滤来处理最少的数据来获得与具有相同坐标的点与最多数据数据相关的最少数量数据来完成的。

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