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1. 发明授权

US08674458B2 Transistors with embedded strain-inducing material formed in cavities provided by an oxidizing etch process 有权
标题翻译：具有嵌入式应变诱导材料的晶体管形成在通过氧化蚀刻工艺提供的空腔中
公开(公告)号：US08674458B2
公开(公告)日：2014-03-18
申请号：US13483630
申请日：2012-05-30
申请人： Stephan-Detlef Kronholz , Rohit Pal , Gunda Beernink
发明人： Stephan-Detlef Kronholz , Rohit Pal , Gunda Beernink
IPC分类号： H01L21/02
CPC分类号： H01L29/7848 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/41775 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7834
摘要： When forming sophisticated semiconductor devices including transistors with sophisticated high-k metal gate electrode structures and a strain-inducing semiconductor alloy, transistor uniformity and performance may be enhanced by providing superior growth conditions during the selective epitaxial growth process. To this end, a semiconductor material may be preserved at the isolation regions in order to avoid the formation of pronounced shoulders. Furthermore, in some illustrative embodiments, additional mechanisms are implemented in order to avoid undue material loss, for instance upon removing a dielectric cap material and the like.
摘要翻译：当形成具有复杂的高k金属栅电极结构的晶体管和应变诱导半导体合金的复杂半导体器件时，可以通过在选择性外延生长工艺期间提供优异的生长条件来增强晶体管的均匀性和性能。为此，可以在隔离区域保留半导体材料，以避免突出的肩部的形成。此外，在一些说明性实施例中，为了避免不适当的材料损失，例如在去除电介质盖材料等时，实施附加机构。

2. 发明申请

US20120306027A1 TRANSISTORS WITH EMBEDDED STRAIN-INDUCING MATERIAL FORMED IN CAVITIES PROVIDED BY AN OXIDIZING ETCH PROCESS 有权
标题翻译：具有嵌入式应变诱导材料的晶体管通过氧化蚀刻工艺提供的CAVIITY
公开(公告)号：US20120306027A1
公开(公告)日：2012-12-06
申请号：US13483630
申请日：2012-05-30
申请人： Stephan-Detlef Kronholz , Rohit Pal , Gunda Beernink
发明人： Stephan-Detlef Kronholz , Rohit Pal , Gunda Beernink
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/41775 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7834
摘要： When forming sophisticated semiconductor devices including transistors with sophisticated high-k metal gate electrode structures and a strain-inducing semiconductor alloy, transistor uniformity and performance may be enhanced by providing superior growth conditions during the selective epitaxial growth process. To this end, a semiconductor material may be preserved at the isolation regions in order to avoid the formation of pronounced shoulders. Furthermore, in some illustrative embodiments, additional mechanisms are implemented in order to avoid undue material loss, for instance upon removing a dielectric cap material and the like.
摘要翻译：当形成具有复杂的高k金属栅电极结构的晶体管和应变诱导半导体合金的复杂半导体器件时，可以通过在选择性外延生长工艺期间提供优异的生长条件来增强晶体管的均匀性和性能。为此，可以在隔离区域保留半导体材料，以避免突出的肩部的形成。此外，在一些说明性实施例中，为了避免不适当的材料损失，例如在去除电介质盖材料等时，实施附加机构。

3. 发明申请

US20120295420A1 SEMICONDUCTOR DEVICES WITH REDUCED STI TOPOGRAPHY BY USING CHEMICAL OXIDE REMOVAL 审中-公开
标题翻译：通过使用化学氧化物去除减少STI天文的半导体器件
公开(公告)号：US20120295420A1
公开(公告)日：2012-11-22
申请号：US13470906
申请日：2012-05-14
申请人： Rohit Pal , Stephan-Detlef Kronholz
发明人： Rohit Pal , Stephan-Detlef Kronholz
IPC分类号： H01L21/20 , H01L21/283
CPC分类号： H01L21/76224 , H01L21/02057 , H01L21/823807 , H01L21/823828 , H01L21/823878 , H01L29/66651 , H01L29/7833
摘要： A thermal oxide may be removed in semiconductor devices prior to performing complex manufacturing processes, such as forming sophisticated gate electrode structures, by using a gaseous process atmosphere instead of a wet chemical etch process, wherein the masking of specific device regions may be accomplished on the basis of a resist mask.
摘要翻译：在通过使用气体处理气氛而不是湿式化学蚀刻工艺执行复杂的制造工艺（例如形成复杂的栅电极结构）之前，可以在半导体器件中去除热氧化物，其中特定器件区域的掩蔽可以在抗蚀剂掩模的基础。

4. 发明申请

US20130040430A1 FORMATION OF A CHANNEL SEMICONDUCTOR ALLOY BY FORMING A NITRIDE BASED HARD MASK LAYER 有权
标题翻译：通过形成基于氮化物的硬掩模层形成通道半导体合金
公开(公告)号：US20130040430A1
公开(公告)日：2013-02-14
申请号：US13552722
申请日：2012-07-19
申请人： Rohit Pal , Stephan-Detlef Kronholz
发明人： Rohit Pal , Stephan-Detlef Kronholz
IPC分类号： H01L21/8234
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823857 , H01L29/665 , H01L29/6656 , H01L29/66651 , H01L29/7833 , H01L29/7848 , Y02P80/30
摘要： The present disclosure provides manufacturing techniques in which sophisticated high-k metal gate electrode structures may be formed in an early manufacturing stage on the basis of a selectively applied threshold voltage adjusting semiconductor alloy. In order to reduce the surface topography upon patterning the deposition mask while still allowing the usage of well-established epitaxial growth recipes developed for silicon dioxide-based hard mask materials, a silicon nitride base material may be used in combination with a surface treatment. In this manner, the surface of the silicon nitride material may exhibit a silicon dioxide-like behavior, while the patterning of the hard mask may be accomplished on the basis of highly selective etch techniques.
摘要翻译：本公开提供了其中可以在选择性施加的阈值电压调节半导体合金的基础上在早期制造阶段中形成复杂的高k金属栅电极结构的制造技术。为了在图案化沉积掩模的同时减少表面形貌，同时仍允许使用为基于二氧化硅的硬掩模材料开发的良好的外延生长配方，可以将氮化硅基材与表面处理组合使用。以这种方式，氮化硅材料的表面可以表现出二氧化硅的行为，而硬掩模的图案化可以基于高选择性蚀刻技术来实现。

5. 发明申请

US20120235245A1 SUPERIOR INTEGRITY OF HIGH-K METAL GATE STACKS BY REDUCING STI DIVOTS BY DEPOSITING A FILL MATERIAL AFTER STI FORMATION 审中-公开
标题翻译：通过在形成气泡之后沉积填充材料来减少STI染色，从而保持高K金属盖板的高度完整性
公开(公告)号：US20120235245A1
公开(公告)日：2012-09-20
申请号：US13422148
申请日：2012-03-16
申请人： Rohit Pal , Stephan-Detlef Kronholz
发明人： Rohit Pal , Stephan-Detlef Kronholz
IPC分类号： H01L27/088 , H01L21/762 , H01L21/336
CPC分类号： H01L21/823481 , H01L21/76232 , H01L21/823878
摘要： When forming sophisticated semiconductor devices on the basis of high-k metal gate electrode structures, which are to be provided in an early manufacturing stage, the encapsulation of the sensitive gate materials may be improved by reducing the depth of or eliminating recessed areas that are obtained after forming sophisticated trench isolation regions. To this end, after completing the STI module, an additional fill material may be provided so as to obtain the desired surface topography and also preserve superior material characteristics of the trench isolation regions.
摘要翻译：当在早期制造阶段提供的高k金属栅极电极结构的基础上形成复杂的半导体器件时，可以通过减少获得的凹陷区域的深度或消除凹陷区域来改善敏感栅极材料的封装形成复杂的沟槽隔离区。为此，在完成STI模块之后，可以提供另外的填充材料以获得所需的表面形貌并且还保持沟槽隔离区域的优良的材料特性。

6. 发明授权

US08664066B2 Formation of a channel semiconductor alloy by forming a nitride based hard mask layer 有权
标题翻译：通过形成氮化物基硬掩模层形成沟道半导体合金
公开(公告)号：US08664066B2
公开(公告)日：2014-03-04
申请号：US13552722
申请日：2012-07-19
申请人： Rohit Pal , Stephan-Detlef Kronholz
发明人： Rohit Pal , Stephan-Detlef Kronholz
IPC分类号： H01L21/8234
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823857 , H01L29/665 , H01L29/6656 , H01L29/66651 , H01L29/7833 , H01L29/7848 , Y02P80/30
摘要： The present disclosure provides manufacturing techniques in which sophisticated high-k metal gate electrode structures may be formed in an early manufacturing stage on the basis of a selectively applied threshold voltage adjusting semiconductor alloy. In order to reduce the surface topography upon patterning the deposition mask while still allowing the usage of well-established epitaxial growth recipes developed for silicon dioxide-based hard mask materials, a silicon nitride base material may be used in combination with a surface treatment. In this manner, the surface of the silicon nitride material may exhibit a silicon dioxide-like behavior, while the patterning of the hard mask may be accomplished on the basis of highly selective etch techniques.
摘要翻译：本公开提供了其中可以在选择性施加的阈值电压调节半导体合金的基础上在早期制造阶段中形成复杂的高k金属栅电极结构的制造技术。为了在图案化沉积掩模的同时减少表面形貌，同时仍允许使用为基于二氧化硅的硬掩模材料开发的良好的外延生长配方，可以将氮化硅基材与表面处理组合使用。以这种方式，氮化硅材料的表面可以表现出二氧化硅的行为，而硬掩模的图案化可以基于高选择性蚀刻技术来实现。

7. 发明授权

US08664057B2 High-K metal gate electrode structures formed by early cap layer adaptation 有权
标题翻译：通过早期盖层适应形成的高K金属栅电极结构
公开(公告)号：US08664057B2
公开(公告)日：2014-03-04
申请号：US13565970
申请日：2012-08-03
申请人： Rohit Pal , Sven Beyer , Andy Wei , Richard Carter
发明人： Rohit Pal , Sven Beyer , Andy Wei , Richard Carter
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/4763 , H01L21/336 , H01L21/28 , H01L21/44 , H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823828
摘要： When forming high-k metal gate electrode structures in transistors of different conductivity type while also incorporating an embedded strain-inducing semiconductor alloy selectively in one type of transistor, superior process uniformity may be accomplished by selectively reducing the thickness of a dielectric cap material of a gate layer stack above the active region of transistors which do not receive the strain-inducing semiconductor alloy. In this case, superior confinement and thus integrity of sensitive gate materials may be accomplished in process strategies in which the sophisticated high-k metal gate electrode structures are formed in an early manufacturing stage, while, in a replacement gate approach, superior process uniformity is achieved upon exposing the surface of a placeholder electrode material.
摘要翻译：当在不同导电类型的晶体管中形成高k金属栅极电极结构时，同时在一种类型的晶体管中选择性地并入嵌入式应变诱导半导体合金，可以通过选择性地减小介电帽材料的厚度来实现优异的工艺均匀性栅极层堆叠在不接收应变诱导半导体合金的晶体管的有源区上方。在这种情况下，可以在早期制造阶段中形成复杂的高k金属栅极电极结构的工艺策略中实现优异的限制和因此敏感栅极材料的完整性，而在替代栅极方法中，优良的工艺均匀性是在暴露观察者电极材料的表面时实现。

8. 发明授权

US08373228B2 Semiconductor transistor device structure with back side source/drain contact plugs, and related manufacturing method 有权
标题翻译：具有背面源极/漏极接触插头的半导体晶体管器件结构及相关制造方法
公开(公告)号：US08373228B2
公开(公告)日：2013-02-12
申请号：US12687607
申请日：2010-01-14
申请人： Bin Yang , Rohit Pal , Michael Hargrove
发明人： Bin Yang , Rohit Pal , Michael Hargrove
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/845 , H01L23/485 , H01L27/12 , H01L27/1211
摘要： A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.
摘要翻译：此处提供制造具有背面导电插头的半导体器件的方法。该方法通过形成覆盖绝缘体上半导体（SOI）衬底的栅极结构开始。 SOI衬底具有支撑层，覆盖在支撑层上的绝缘层，覆盖绝缘层的有源半导体区域和有源半导体区域外侧的隔离区域。栅极结构的第一部分形成在隔离区域的上方，栅极结构的第二部分形成在有源半导体区域的上方。该方法通过在有源半导体区域中形成源极/漏极区域继续，然后从SOI衬底去除支撑层。接下来，该方法形成用于栅极结构和源极/漏极区域的导电插塞，其中每个导电插塞穿过绝缘层。

9. 发明申请

US20130032893A1 SEMICONDUCTOR DEVICE COMPRISING METAL GATE ELECTRODE STRUCTURES AND NON-FETS WITH DIFFERENT HEIGHT BY EARLY ADAPTATION OF GATE STACK TOPOGRAPHY 审中-公开
标题翻译：包含金属栅极电极结构和不同高度的非FET的半导体器件通过栅格堆叠拓扑的早期适应
公开(公告)号：US20130032893A1
公开(公告)日：2013-02-07
申请号：US13550693
申请日：2012-07-17
申请人： Rohit Pal , George Mulfinger
发明人： Rohit Pal , George Mulfinger
IPC分类号： H01L27/088 , H01L21/283
CPC分类号： H01L23/5256 , H01L23/485 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： Gate height scaling in sophisticated semiconductor devices may be implemented without requiring a redesign of non-transistor devices. To this end, the semiconductor electrode material may be adapted in its thickness above active regions and isolation regions that receive the non-transistor devices. Thereafter, the actual patterning of the adapted gate layer stack may be performed so as to obtain gate electrode structures of a desired height for improving, in particular, AC performance without requiring a redesign of the non-transistor devices.
摘要翻译：可以实现复杂半导体器件中的栅极高度缩放，而不需要重新设计非晶体管器件。为此，可以将半导体电极材料的厚度适用于有源区域和接收非晶体管器件的隔离区域。此后，可以执行适合的栅极层堆叠的实际图案化，以获得所需高度的栅电极结构，以改善特别是AC性能，而不需要重新设计非晶体管器件。

10. 发明申请

US20120193727A1 ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A GATE DIELECTRIC CAP LAYER MATERIAL PRIOR TO GATE DIELECTRIC STABILIZATION 有权
标题翻译：通过扩大栅极电介质层材料来调节放电晶体管的栅极电压以进行电介质稳定化
公开(公告)号：US20120193727A1
公开(公告)日：2012-08-02
申请号：US13444955
申请日：2012-04-12
申请人： Richard Carter , Martin Trentzsch , Sven Beyer , Rohit Pal
发明人： Richard Carter , Martin Trentzsch , Sven Beyer , Rohit Pal
IPC分类号： H01L27/088
CPC分类号： H01L21/823462 , H01L21/28176 , H01L21/28194 , H01L29/513 , H01L29/517
摘要： Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.
摘要翻译：复杂的栅极电极结构可以通过在进行用于稳定敏感栅极介电材料的处理之前提供包括可能扩散到栅极电介质材料中的所需物质的覆盖层来形成。以这种方式，与常规策略相比，可以基于用于阈值调节物质的降低的温度和剂量来形成复杂的高k金属栅电极结构。此外，可以为两种类型的晶体管沉积单个含金属的电极材料。

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