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1. 发明授权

US06589364B1 Formation of doped silicon-germanium alloy utilizing laser crystallization 有权
标题翻译：利用激光结晶形成掺杂硅锗合金
公开(公告)号：US06589364B1
公开(公告)日：2003-07-08
申请号：US09620635
申请日：2000-07-20
申请人： Stepan Essaian , Abdalla A. Naem
发明人： Stepan Essaian , Abdalla A. Naem
IPC分类号： H01L2120
CPC分类号： H01L21/02686 , C30B13/00 , C30B29/52 , H01L21/2026 , H01L21/268 , H01L29/66242
摘要： A silicon-germanium alloy of high crystal quality and containing uniform concentrations of dopant and germanium is formed by applying laser energy to a doped amorphous/polysilicon germanium layer overlying epitaxial silicon. Energy transferred from the laser beam causes melting of the germanium and the underlying silicon, resulting in diffusion of germanium and dopant into the melted silicon. Subsequent cooling and crystallization of the silicon/germanium/dopant melt produces a high quality crystal lattice uniformly incorporating germanium and dopant within its structure. Efficient energy transfer from the laser beam to the underlying germanium and silicon may be promoted by patterning an anti-reflective coating over the amorphous/polysilicon doped germanium prior to exposure to laser radiation. The process is particularly suited for forming the silicon-germanium base of a heterojunction bipolar transistor device.
摘要翻译：通过将激光能量施加到覆盖外延硅的掺杂非晶/多晶硅锗层上，形成高质量并含有均匀浓度的掺杂剂和锗的硅锗合金。从激光束转移的能量导致锗和下面的硅熔化，导致锗和掺杂剂扩散到熔融的硅中。硅/锗/掺杂剂熔体的随后冷却和结晶产生在其结构内均匀掺入锗和掺杂剂的高质量晶格。可以通过在暴露于激光辐射之前在非晶/多晶硅掺杂的锗上图案化抗反射涂层来促进从激光束到下面的锗和硅的有效能量传递。该方法特别适用于形成异质结双极晶体管器件的硅 - 锗基底。

2. 发明授权

US06355544B1 Selective high concentration doping of semiconductor material utilizing laser annealing 有权
标题翻译：使用激光退火的半导体材料的选择性高浓度掺杂
公开(公告)号：US06355544B1
公开(公告)日：2002-03-12
申请号：US09620481
申请日：2000-07-20
申请人： Stepan Essaian , Abdalla A. Naem
发明人： Stepan Essaian , Abdalla A. Naem
IPC分类号： H01L2126
CPC分类号： H01L21/2251 , H01L21/268 , H01L21/428
摘要： Extremely high dopant concentrations are uniformly introduced into a semiconductor material by laser annealing aided by an anti-reflective coating (ARC). A spin-on-glass (SOG) film containing dopant is formed on top of the semiconductor material. An ARC is then formed over the doped SOG layer. Application of radiation from an excimer laser to the ARC heats and melts the doped SOG film and the underlying semiconductor material. During this melting process, dopant from the SOG film diffuses uniformly within the semiconductor material. Upon removal of the laser radiation, the semiconductor material cools and crystallizes, evenly incorporating the diffused dopant within its lattice structure. The ARC suppresses reflection of the laser by the doped material, promoting efficient transfer of energy from the laser to heat and melt the underlying doped layer and semiconductor material. The present process is especially suited for introducing extremely high levels of conductivity-altering dopant (1020-1021 atoms/cm3) into the polysilicon emitter of a heterojunction bipolar transistor device.
摘要翻译：通过由抗反射涂层（ARC）辅助的激光退火将非常高的掺杂剂浓度均匀地引入到半导体材料中。在半导体材料的顶部形成含有掺杂剂的旋涂玻璃（SOG）膜。然后在掺杂的SOG层上形成ARC。将来自准分子激光器的辐射施加到ARC加热并熔化掺杂的SOG膜和下面的半导体材料。在该熔融过程中，来自SOG膜的掺杂剂在半导体材料内均匀扩散。在去除激光辐射后，半导体材料冷却并结晶，均匀地掺入扩散掺杂剂在其晶格结构内。 ARC通过掺杂材料抑制激光的反射，促进能量从激光器的有效转移到加热并熔化下面的掺杂层和半导体材料。本方法特别适用于将非常高水平的导电性改变掺杂剂（1020-1021原子/ cm3）引入到异质结双极晶体管器件的多晶硅发射极中。

3. 发明授权

US4680609A Structure and fabrication of vertically integrated CMOS logic gates 失效
标题翻译：垂直集成CMOS逻辑门的结构和制造
公开(公告)号：US4680609A
公开(公告)日：1987-07-14
申请号：US653192
申请日：1984-09-24
申请人： Iain D. Calder , Thomas W. Macelwee , Abdalla A. Naem
发明人： Iain D. Calder , Thomas W. Macelwee , Abdalla A. Naem
IPC分类号： H01L27/06 , H01L27/02 , H01L29/04 , H01L29/78
CPC分类号： H01L27/0688
摘要： A vertically integrated CMOS logic gate has spaced semiconductor layers with control gates located between the layers and insulated from them by gate oxide. Transistors formed in one semiconductor layer are vertically aligned with transistors formed in the other semiconductor layer. Pairs of vertically coincident transistors have common control gates and certain of the pairs have integral drain regions. Transistors in one layer are series connected in an open loop configuration and transistors in the other layer are parallel connected in a closed loop configuration. The logic gate function depends on voltages applied to the common control gates and to the open and closed loops. By the vertical integration, a two-input NAND or NOR gate can be made using less area than that required for two simple MOS transistors.
摘要翻译：垂直集成的CMOS逻辑门具有间隔开的半导体层，其中控制栅极位于层之间并与栅极氧化物绝缘。形成在一个半导体层中的晶体管与形成在另一半导体层中的晶体管垂直对准。一对垂直重合的晶体管具有公共控制栅极，并且一些对具有整体漏极区域。一层中的晶体管以开环配置串联连接，另一层的晶体管以闭环配置并联。逻辑门功能取决于施加到公共控制门和开环和闭环的电压。通过垂直积分，可以使用比两个简单的MOS晶体管所需的面积小的面积来制作双输入NAND或者或非门。

4. 发明授权

US4476475A Stacked MOS transistor 失效
标题翻译：堆叠MOS晶体管
公开(公告)号：US4476475A
公开(公告)日：1984-10-09
申请号：US442864
申请日：1982-11-19
申请人： Abdalla A. Naem , Hussein M. Naguib , Iain D. Calder , Albert R. Boothroyd
发明人： Abdalla A. Naem , Hussein M. Naguib , Iain D. Calder , Albert R. Boothroyd
IPC分类号： H01L21/268 , H01L21/822 , H01L27/06 , H01L29/78 , H01L27/02 , H01L29/04
CPC分类号： H01L27/0688 , H01L21/268 , H01L21/8221
摘要： In a stacked metal-oxide-semiconductor (SMOS) transistor, the transistor source, drain and channel each have a lower part formed in a silicon substrate and an upper part composed of recrystallized polysilicon. The device gate is located between the upper and lower channel parts. By vertically integrating a MOS transistor, performance limitations imposed by the direct scaling approach to device miniaturization are avoided.
摘要翻译：在堆叠的金属氧化物半导体（SMOS）晶体管中，晶体管源极，漏极和沟道各自具有形成在硅衬底中的下部和由再结晶多晶硅组成的上部。设备门位于上部和下部通道部分之间。通过垂直集成MOS晶体管，避免了直接缩放方法对器件小型化所产生的性能限制。

5. 发明授权

US06406966B1 Uniform emitter formation using selective laser recrystallization 有权
标题翻译：使用选择性激光重结晶均匀的发射体形成
公开(公告)号：US06406966B1
公开(公告)日：2002-06-18
申请号：US09708261
申请日：2000-11-07
申请人： Abdalla A. Naem
发明人： Abdalla A. Naem
IPC分类号： H01L21331
CPC分类号： H01L29/66272 , H01L21/02532 , H01L21/02664 , H01L21/2026 , H01L29/0804
摘要： Method is provided for forming an emitter structure in a semiconductor integrated circuit bipolar transistor structure. The bipolar transistor structure includes a collector region that has a first conductivity type formed in a semiconductor substrate and a base region having a second conductivity type, opposite the first conductivity type, formed in the collector region. A layer of dielectric material is formed on the surface of the base region. An emitter window is opened in the layer of dielectric material to expose a surface area of the base region. A layer of conductive material is then formed over the layer of dielectric material and extending into the emitter window such that at least a portion of the layer of conductive material is in contact with the surface area of the base region. Dopant of the first conductivity type is then introduced into the layer of conductive material. A region of anti-reflective coating (ARC) material is formed on the layer of conductive material over the emitter window opening such that portions of the layer of the conductive material are exposed. Sufficient laser energy is then applied to the structure resulting from the foregoing steps to cause the conductive material underlying the region of anti-reflective coating material to flow. The region of anti-reflective coating material is then removed and the conductive material is patterned to define an emitter region that extends into the emitter window opening and in interfacial contact with the surface area of the base region.
摘要翻译：提供了用于在半导体集成电路双极晶体管结构中形成发射极结构的方法。双极晶体管结构包括形成在集电区域中的具有形成在半导体衬底中的第一导电类型和与第一导电类型相反的第二导电类型的基极区域的集电极区域。在基底区域的表面上形成介电材料层。在介电材料层中打开发射器窗口以暴露基极区域的表面区域。然后在电介质材料层上形成一层导电材料，并延伸到发射器窗口，使得导电材料层的至少一部分与基极区域的表面区域接触。然后将第一导电类型的掺杂剂引入到导电材料层中。在发射器窗口的导电材料层上形成防反射涂层（ARC）材料区域，使得导电材料层的部分露出。然后将足够的激光能量施加到由上述步骤导致的结构，以使得位于抗反射涂层材料区域下方的导电材料流动。然后去除抗反射涂层材料的区域，并且将导电材料图案化以限定延伸到发射器窗口内并与基底区域的表面区域界面接触的发射极区域。

6. 发明授权

US5843834A Self-aligned POCL.sub.3 process flow for submicron microelectronics applications using amorphized polysilicon 失效
标题翻译：使用非晶化多晶硅的亚微米微电子应用的自对准POCL3工艺流程
公开(公告)号：US5843834A
公开(公告)日：1998-12-01
申请号：US689334
申请日：1996-08-08
申请人： Abdalla A. Naem
发明人： Abdalla A. Naem
IPC分类号： H01L21/28 , H01L21/336 , H01L21/225
CPC分类号： H01L29/6659 , H01L21/28052
摘要： In a method of introducing phosphorous into an undoped gate polysilicon region formed as part of an integrated circuit structure, an initial MOS structure is developed utilizing conventional techniques through the lightly doped drain (LDD) implant step, with the exception, that, in this case, the gate polysilicon remains undoped. In accordance with the invention, dopant is then implanted into the source/drain regions such that the undoped gate polysilicon is amorphized, thereby eliminating the polysilicon grain boundaries. A CVD oxide layer is then formed and a CMP step is performed to expose the amorphized gate polysilicon region. A phosphorous oxychloride (POCl.sub.3) layer is then formed over the amorphized gate polysilicon and thermally annealed to drive phosphorous from the POCl.sub.3 layer into the polysilicon. The POCl.sub.3 layer is then removed.
摘要翻译：在将磷引入到作为集成电路结构的一部分形成的未掺杂栅极多晶硅区域的方法中，使用常规技术通过轻掺杂漏极（LDD）注入步骤开发初始MOS结构，除了在这种情况下，栅极多晶硅保持未掺杂。根据本发明，然后将掺杂剂注入到源极/漏极区域中，使得未掺杂的栅极多晶硅非晶化，从而消除多晶硅晶界。然后形成CVD氧化物层，并执行CMP步骤以暴露非晶化栅极多晶硅区域。然后在非晶化栅极多晶硅上形成磷酰氯（POCl 3）层并热退火以将磷从POCl 3层驱动到多晶硅中。然后除去POCl 3层。

7. 发明授权

US4683645A Process of fabricating MOS devices having shallow source and drain junctions 失效
标题翻译：制造具有浅源极和漏极结的MOS器件的工艺
公开(公告)号：US4683645A
公开(公告)日：1987-08-04
申请号：US813232
申请日：1985-12-24
申请人： Hussein M. Naguib , Iain D. Calder , Vu Q. Ho , Abdalla A. Naem
发明人： Hussein M. Naguib , Iain D. Calder , Vu Q. Ho , Abdalla A. Naem
IPC分类号： H01L21/265 , H01L21/285 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66575 , H01L21/26506 , H01L21/2652 , H01L21/28518 , Y10S148/14
摘要： In a metal oxide semiconductor field effect transistor fabrication process, refractory metal is deposited over designated source and drain areas within a silicon substrate. Refractory metal and silicon at the interface is then mixed by ion implantation of a heavy neutral ion species such as germanium. To minimize source/drain junction depth, the source and drain locations can be subjected to bombardment by a lighter ion such as silicon which amorphizes silicon to a predetermined depth under the designated source and drain regions and so substantially confines dopant diffusion to the silicon amorphized region. To render the source and drain of desired conductivity type, an ion implantation of a non-neutral ion is then performed.
摘要翻译：在金属氧化物半导体场效应晶体管制造工艺中，难熔金属沉积在硅衬底内的指定源极和漏极区域上。然后在界面处的耐火金属和硅通过离子注入重质中性离子物质如锗混合。为了使源极/漏极结深度最小化，源极和漏极位置可以被诸如硅之类的较轻的离子轰击，使得硅在指定的源极和漏极区域之下将硅非晶化至预定深度，因此基本上将掺杂剂扩散限制到硅非晶化区域。为了使所需导电类型的源极和漏极，然后执行非中性离子的离子注入。

8. 发明授权

US5824596A POCl.sub.3 process flow for doping polysilicon without forming oxide pillars or gate oxide shorts 失效
标题翻译： POCl3工艺流程用于掺杂多晶硅而不形成氧化物柱或栅极氧化物短路
公开(公告)号：US5824596A
公开(公告)日：1998-10-20
申请号：US689335
申请日：1996-08-08
申请人： Abdalla A. Naem
发明人： Abdalla A. Naem
IPC分类号： H01L21/28 , H01L29/49 , H02L21/77
CPC分类号： H01L21/28035 , H01L29/4916
摘要： In a method of introducing phosphorous from phosphorous oxychloride (POCl.sub.3) into an undoped gate polysilicon region formed as part of an integrated circuit structure, an initial MOS structure is developed utilizing conventional techniques through the formation of a layer of undoped polysilicon over thin gate oxide. A POCl.sub.3 layer is then formed over the undoped polysilicon and thermally annealed to drive phosphorous into the gate polysilicon to achieve a desired conductivity level. The phosphorous-rich organic layer is then cleaned from the surface of the POCl.sub.3 using sulfuric peroxide and the POCl.sub.3 layer is removed using a DI:HF solution to expose the surface of the doped polysilicon. After formation of a photoresist gate mask, arsenic, or another heavy ion species, is implanted into the exposed polysilicon to amorphized the exposed poly, thereby eliminating the polysilicon grain boundaries. This leads to uniform etching of the amorphized poly and, therefore, disappearance of the oxide pillars. Removal of the organic layer from the POCl.sub.3 Layer prior to the HF deglaze step facilitates smooth, uniform etching of the POCl.sub.3 in reduced time, thereby eliminating the gate oxide holes experienced in the conventional process flow.
摘要翻译：在从磷酰氯（POCl 3）中引入磷到作为集成电路结构的一部分形成的未掺杂的栅极多晶硅区域的方法中，利用常规技术通过在薄栅极氧化物上形成未掺杂的多晶硅层来开发初始MOS结构。然后在未掺杂多晶硅上形成POCl 3层，并进行热退火以将磷驱动到栅极多晶硅中以实现期望的导电性水平。然后使用硫酸过氧化物从POCl 3的表面清洗富磷有机层，并使用DI：HF溶液除去POCl 3层以暴露掺杂多晶硅的表面。在形成光致抗蚀剂掩模之后，将砷或另一种重离子种类注入到暴露的多晶硅中以将暴露的多晶硅非晶化，从而消除多晶硅晶界。这导致了非晶化聚合物的均匀蚀刻，并因此导致氧化物柱的消失。在HF脱气步骤之前从POCl 3层去除有机层有助于在缩短的时间内平滑地均匀地蚀刻POCl 3，从而消除常规工艺流程中经历的栅极氧化物孔。

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