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1. 发明授权

US08198929B2 Dynamic element matching for time-to-digital converters 有权
标题翻译：时间 - 数字转换器的动态元件匹配
公开(公告)号：US08198929B2
公开(公告)日：2012-06-12
申请号：US12872993
申请日：2010-08-31
申请人： Stefano Pellerano , Paolo Madoglio , Ashoke Ravi
发明人： Stefano Pellerano , Paolo Madoglio , Ashoke Ravi
IPC分类号： H03L7/06
CPC分类号： H03L7/1974 , H03L2207/50
摘要： Embodiments of the present disclosure provide methods, systems, and apparatuses related to dynamic element matching for time-to-digital converters. Other embodiments may be described and claimed.
摘要翻译：本公开的实施例提供了与时间 - 数字转换器的动态元件匹配相关的方法，系统和装置。可以描述和要求保护其他实施例。

2. 发明申请

US20150181643A1 DIRECT DIGITAL FREQUENCY GENERATION USING TIME AND AMPLITUDE 有权
标题翻译：使用时间和幅度的直接数字频率生成
公开(公告)号：US20150181643A1
公开(公告)日：2015-06-25
申请号：US14138508
申请日：2013-12-23
申请人： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Bernd-Ulrich Klepser , Zdravko Boos , Georgios Palaskas , Stefano Pellerano , Paolo Madoglio
发明人： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Bernd-Ulrich Klepser , Zdravko Boos , Georgios Palaskas , Stefano Pellerano , Paolo Madoglio
IPC分类号： H04W88/06 , H04L27/20 , H04B7/06
CPC分类号： H04L7/033 , H03K2005/00234 , H03L7/16 , H04B7/0413 , H04B7/06 , H04L27/152 , H04L27/1525 , H04L27/20 , H04W88/06
摘要： This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.
摘要翻译：本应用程序还讨论了用于在多个无线设备之间共享本地振荡器的装置和方法。在某些示例中，装置可以包括配置成提供具有第一频率的中心振荡器信号的中央频率合成器，第一发射机，第一发射机包括被配置为接收中心振荡器的第一发射数字 - 时间转换器（DTC）并且提供具有第二频率的第一发射机信号和第一接收机，所述第一接收机包括被配置为接收中心振荡器信号并提供具有第一接收频率的第一接收机信号的第一接收DTC。

3. 发明申请

US20120049914A1 DYNAMIC ELEMENT MATCHING FOR TIME-TO-DIGITAL CONVERTERS 有权
标题翻译：用于时间到数字转换器的动态元件匹配
公开(公告)号：US20120049914A1
公开(公告)日：2012-03-01
申请号：US12872993
申请日：2010-08-31
申请人： Stefano Pellerano , Paolo Madoglio , Ashoke Ravi
发明人： Stefano Pellerano , Paolo Madoglio , Ashoke Ravi
IPC分类号： H03L7/06
CPC分类号： H03L7/1974 , H03L2207/50
摘要： Embodiments of the present disclosure provide methods, systems, and apparatuses related to dynamic element matching for time-to-digital converters. Other embodiments may be described and claimed.
摘要翻译：本公开的实施例提供了与时间 - 数字转换器的动态元件匹配相关的方法，系统和装置。可以描述和要求保护其他实施例。

4. 发明申请

US20100156485A1 DELAY ELEMENT ARRAY FOR TIME-TO-DIGITAL CONVERTERS 有权
标题翻译：延迟元件阵列用于时间到数字转换器
公开(公告)号：US20100156485A1
公开(公告)日：2010-06-24
申请号：US12342443
申请日：2008-12-23
申请人： Paolo Madoglio , Stefano Pellerano
发明人： Paolo Madoglio , Stefano Pellerano
IPC分类号： H03L7/06
CPC分类号： H03L7/08 , H03L2207/50
摘要： Embodiments of the present disclosure provide methods, systems, and apparatuses related to a delay element array for time-to-digital converters. Some embodiments include a voltage controlled oscillator; a time-to-digital converter including a delay element array to output delayed versions of a signal and logic to generate a digital word that represents phase information of the signal based at least in part on the delayed versions; and a phase detector to generate a digital phase error based at least in part on the digital word. Other embodiments may be described and claimed.
摘要翻译：本公开的实施例提供了与用于时间 - 数字转换器的延迟元件阵列有关的方法，系统和装置。一些实施例包括压控振荡器; 时间数字转换器，包括延迟元件阵列以输出信号的延迟版本和逻辑，以至少部分地基于所述延迟版本来生成表示所述信号的相位信息的数字字; 以及相位检测器，用于至少部分地基于数字字产生数字相位误差。可以描述和要求保护其他实施例。

5. 发明申请

US20150156044A1 PARALLEL DIGITAL-TO-TIME CONVERTER ARCHITECTURE 有权
标题翻译：并行数字时间转换器架构
公开(公告)号：US20150156044A1
公开(公告)日：2015-06-04
申请号：US14096464
申请日：2013-12-04
申请人： Paolo Madoglio , Stefano Pellerano
发明人： Paolo Madoglio , Stefano Pellerano
IPC分类号： H04L27/20 , H04L27/22 , H03M1/68 , H03M1/82 , H03M1/74
CPC分类号： H04L27/20 , H04L27/22
摘要： This document discusses, among other things, digital-to-time converters (DTCs) and more particularly to parallel implementations of DTCs. In an example, an apparatus can include a first digital-to-time converter (DTC) configured to receive reference frequency information and first phase information of a polar transmitter and to provide a first portion of phase modulation information, a second DTC configured to receive second phase information of the polar transmitter and to provide a second portion of phase modulation information, and a combiner configured to receive the first portion and the second portion and to provide a phase modulated signal.
摘要翻译：本文件尤其涉及数字到时间转换器（DTC），特别是DTC的并行实现。在一个示例中，设备可以包括被配置为接收极性发射机的参考频率信息和第一相位信息并提供第一部分相位调制信息的第一数字 - 时间转换器（DTC），第二DTC被配置为接收并且提供相位调制信息的第二部分，以及配置成接收第一部分和第二部分并且提供相位调制信号的组合器。

6. 发明授权

US08598930B2 Digital delay-locked loop with drift sensor 有权
标题翻译：具有漂移传感器的数字延迟锁定环
公开(公告)号：US08598930B2
公开(公告)日：2013-12-03
申请号：US13995472
申请日：2011-08-23
申请人： Stefano Pellerano , Paolo Madoglio
发明人： Stefano Pellerano , Paolo Madoglio
IPC分类号： H03L7/06
CPC分类号： H03L7/148 , H03L7/0814 , H03L7/0816
摘要： Embodiments of the present disclosure provide methods, systems, and apparatuses related to an open-loop digital delay-locked loop having a drift sensor. Other embodiments may be described and claimed.
摘要翻译：本公开的实施例提供了与具有漂移传感器的开环数字延迟锁定环相关的方法，系统和装置。可以描述和要求保护其他实施例。

7. 发明申请

US20130271194A1 DIGITAL DELAY-LOCKED LOOP WITH DRIFT SENSOR 有权
标题翻译：带DRIFT传感器的数字延迟锁定环
公开(公告)号：US20130271194A1
公开(公告)日：2013-10-17
申请号：US13995472
申请日：2011-08-23
申请人： Stefano Pellerano , Paolo Madoglio
发明人： Stefano Pellerano , Paolo Madoglio
IPC分类号： H03L7/14
CPC分类号： H03L7/148 , H03L7/0814 , H03L7/0816
摘要： Embodiments of the present disclosure provide methods, systems, and apparatuses related to an open-loop digital delay-locked loop having a drift sensor. Other embodiments may be described and claimed.
摘要翻译：本公开的实施例提供了与具有漂移传感器的开环数字延迟锁定环相关的方法，系统和装置。可以描述和要求保护其他实施例。

8. 发明授权

US07782104B2 Delay element array for time-to-digital converters 有权
标题翻译：用于时间 - 数字转换器的延迟元件阵列
公开(公告)号：US07782104B2
公开(公告)日：2010-08-24
申请号：US12342443
申请日：2008-12-23
申请人： Paolo Madoglio , Stefano Pellerano
发明人： Paolo Madoglio , Stefano Pellerano
IPC分类号： H03L7/06
CPC分类号： H03L7/08 , H03L2207/50
摘要： Embodiments of the present disclosure provide methods, systems, and apparatuses related to a delay element array for time-to-digital converters. Some embodiments include a voltage controlled oscillator; a time-to-digital converter including a delay element array to output delayed versions of a signal and logic to generate a digital word that represents phase information of the signal based at least in part on the delayed versions; and a phase detector to generate a digital phase error based at least in part on the digital word. Other embodiments may be described and claimed.
摘要翻译：本公开的实施例提供了与用于时间 - 数字转换器的延迟元件阵列有关的方法，系统和装置。一些实施例包括压控振荡器; 时间数字转换器，包括延迟元件阵列以输出信号的延迟版本和逻辑，以至少部分地基于所述延迟版本来生成表示所述信号的相位信息的数字字; 以及相位检测器，用于至少部分地基于数字字产生数字相位误差。可以描述和要求保护其他实施例。

9. 发明申请

US20080070512A1 Offset-frequency loop-back calibration 有权
标题翻译：偏移环回校准
公开(公告)号：US20080070512A1
公开(公告)日：2008-03-20
申请号：US11522599
申请日：2006-09-18
申请人： Georgios Palaskas , Stefano Pellerano , Ashoke Ravi
发明人： Georgios Palaskas , Stefano Pellerano , Ashoke Ravi
IPC分类号： H04B1/44
CPC分类号： H03F1/32 , H03F1/34 , H03F3/24 , H03F2200/321 , H03F2200/451 , H04B2001/0433
摘要： Embodiments of methods and means for calibrating a linearization characteristic within an RF transceiver system are provided. Such embodiments generally include extracting a portion of an output signal and frequency shifting or translating that signal by a predetermined value. The frequency shifted signal is then summed or otherwise introduced into a receiver signal pathway where it is analyzed by digital signal processing or other means to determine if linearization distortion is present. Linearization calibration of a power amplifier, a low-noise amplifier and/or other functionality within the system can then be performed in an automatic, reliable and ongoing manner.
摘要翻译：提供了用于校准RF收发器系统内的线性化特性的方法和装置的实施例。这样的实施例通常包括提取输出信号的一部分并将该信号频移或转换预定值。然后将频移信号相加或以其他方式引入到接收机信号路径中，其中通过数字信号处理或其他手段来分析，以确定是否存在线性化失真。然后可以以自动，可靠和持续的方式执行系统内的功率放大器，低噪声放大器和/或其他功能的线性化校准。

10. 发明授权

US07907018B2 Phase noise minimized phase/frequency-locked voltage-controlled oscillator circuit 有权
标题翻译：相位噪声最小相/锁频压控振荡电路
公开(公告)号：US07907018B2
公开(公告)日：2011-03-15
申请号：US12579149
申请日：2009-10-14
申请人： Stefano Pellerano , Ashoke Ravi , Yorgos Palaskas
发明人： Stefano Pellerano , Ashoke Ravi , Yorgos Palaskas
IPC分类号： H03L7/099
CPC分类号： H03L7/099 , H03L7/0995 , H03L7/18 , H03L2207/06
摘要： A phase noise minimization circuit is disclosed, to be used in a voltage-controlled oscillator (VCO) circuit embedded in a feedback system. The phase noise minimization circuit includes a noise power meter to analyze the control voltage fed into the VCO by the feedback system and determine its voltage noise power. Since the VCO is controlled by the feedback system, the control voltage noise power is also an indication of the VCO phase noise power for frequencies offset within the bandwidth of the feedback system. The VCO has several parameters that can be adjusted to affect its phase noise. A minimization algorithm generates the optimum set of parameters that minimize the control voltage noise power (and thus the VCO phase noise power), and sends them to the oscillator. The phase noise minimization circuit may be used in a variety of applications, particularly in phase-locked loop and frequency-locked loop VCOs.
摘要翻译：公开了一种用于嵌入在反馈系统中的压控振荡器（VCO）电路中的相位噪声最小化电路。相位噪声最小化电路包括噪声功率计，用于分析由反馈系统馈送到VCO的控制电压并确定其电压噪声功率。由于VCO由反馈系统控制，所以控制电压噪声功率也是在反馈系统的带宽内偏移的频率的VCO相位噪声功率的指示。 VCO具有几个参数，可以调整以影响其相位噪声。最小化算法生成最小化控制电压噪声功率（从而使VCO相位噪声功率）最小化的最佳参数集，并将其发送到振荡器。相位噪声最小化电路可以用于各种应用中，特别是在锁相环和锁相环VCO中。

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