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1. 发明授权

US08402403B2 Verifying a register-transfer level design of an execution unit 有权
标题翻译：验证执行单元的寄存器传输级设计
公开(公告)号：US08402403B2
公开(公告)日：2013-03-19
申请号：US12946325
申请日：2010-11-15
申请人： Stefan Letz , Michelangelo Masini , Juergen Vielfort , Kai Weber
发明人： Stefan Letz , Michelangelo Masini , Juergen Vielfort , Kai Weber
IPC分类号： G06F17/50 , G06F9/455 , G06G7/62
CPC分类号： G06F17/5022 , G06F17/505
摘要： A mechanism is provided for verifying a register-transfer level design of an execution unit. A set of instruction records associated with a test case are generated and stored in a buffer. For each instruction record in the set of instruction records associated with the test case: the instruction record is retrieved from the buffer and sent to both a reference model and an execution unit in the data processing system. Separately, the reference model and the execution unit execute the instruction record and send results of the execution of the instruction record to a result checker in the data processing system. The result checker compares the two results and, responsive to a mismatch in the results, a failure of the test case is indicted, the verification of the test case is stopped, and all data associated with the test case is output from the buffer for analysis.
摘要翻译：提供了一种用于验证执行单元的寄存器传送级别设计的机制。生成与测试用例相关联的一组指令记录并将其存储在缓冲器中。对于与测试用例相关联的指令记录集中的每个指令记录：从缓冲器检索指令记录并发送给数据处理系统中的参考模型和执行单元。另外，参考模型和执行单元执行指令记录并将执行指令记录的结果发送到数据处理系统中的结果检查器。结果检查器比较两个结果，并且响应于结果不匹配，指示测试用例的失败，测试用例的验证被停止，并且与测试用例相关联的所有数据从缓冲器输出用于分析。

2. 发明申请

US20110154110A1 Verifying a Register-Transfer Level Design of an Execution Unit 有权
标题翻译：验证执行单位的注册级别转移级别设计
公开(公告)号：US20110154110A1
公开(公告)日：2011-06-23
申请号：US12946325
申请日：2010-11-15
申请人： Stefan Letz , Michelangelo Masini , Juergen Vielfort , Kai Weber
发明人： Stefan Letz , Michelangelo Masini , Juergen Vielfort , Kai Weber
IPC分类号： G06F11/26
CPC分类号： G06F17/5022 , G06F17/505
摘要： A mechanism is provided for verifying a register-transfer level design of an execution unit a set of instruction records associated with a test case are generated and stored in a buffer. For each instruction record in the set of instruction records associated with the test case: the instruction record is retrieved from the buffer and sent to both a reference model and an execution unit in the data processing system. Separately, the reference model and the execution unit execute the instruction record and send results of the execution of the instruction record to a result checker in the data processing system. The result checker compares the two results and, responsive to a mismatch in the results, a failure of the test case is indicted, the verification of the test case is stopped, and all data associated with the test case is output from the buffer for analysis,
摘要翻译：提供了一种用于验证执行单元的寄存器传送级别设计的机制，与测试用例相关联的一组指令记录被生成并存储在缓冲器中。对于与测试用例相关联的指令记录集中的每个指令记录：从缓冲器检索指令记录并发送给数据处理系统中的参考模型和执行单元。另外，参考模型和执行单元执行指令记录并将执行指令记录的结果发送到数据处理系统中的结果检查器。结果检查器比较两个结果，并且响应于结果不匹配，指示测试用例的失败，测试用例的验证被停止，并且与测试用例相关联的所有数据从缓冲器输出用于分析，

3. 发明授权

US08249848B2 Verifying a processor design using a processor simulation model 有权
标题翻译：使用处理器仿真模型验证处理器设计
公开(公告)号：US08249848B2
公开(公告)日：2012-08-21
申请号：US12182211
申请日：2008-07-30
申请人： Stefan Letz , Kai Weber , Juergen Vielfort
发明人： Stefan Letz , Kai Weber , Juergen Vielfort
IPC分类号： G06F17/50
CPC分类号： G06F9/3859 , G06F17/5022 , G06F2217/68
摘要： An improved method of verifying a processor design using a processor simulation model in a simulation environment is disclosed, wherein the processor simulation model includes at least one execution unit for executing at least one instruction of a test file. The method includes tracking each execution of each of the at least one instruction, monitoring relevant signals in each simulation cycle, maintaining information about the execution of the at least one instruction, wherein the maintained information includes a determination of an execution length of a completely executed instruction, matching the maintained information about the completely executed instruction against a set of trap elements provided by the user through a trap file, and collecting the maintained information about the completely executed instruction in a monitor file in response to a match found between the maintained information and at least one of the trap elements.
摘要翻译：公开了一种使用仿真环境中的处理器仿真模型验证处理器设计的改进方法，其中所述处理器仿真模型包括用于执行测试文件的至少一个指令的至少一个执行单元。该方法包括跟踪每个执行至少一个指令中的每一个，监视每个模拟周期中的相关信号，维护关于至少一个指令的执行的信息，其中维护的信息包括完全执行的执行长度的确定指令，将关于完全执行的指令的维护信息与由用户通过陷阱文件提供的一组陷阱元素相匹配，并且响应于在维护信息之间找到的匹配而将关于完全执行的指令的维护信息收集在监视文件中和至少一个捕获元件。

4. 发明授权

US08600724B2 Verifying a processor design using a processor simulation model 失效
标题翻译：使用处理器仿真模型验证处理器设计
公开(公告)号：US08600724B2
公开(公告)日：2013-12-03
申请号：US13552634
申请日：2012-07-18
申请人： Stefan Letz , Kai Weber , Juergen Vielfort
发明人： Stefan Letz , Kai Weber , Juergen Vielfort
IPC分类号： G06F17/50
CPC分类号： G06F9/3859 , G06F17/5022 , G06F2217/68
摘要： An improved method of verifying a processor design using a processor simulation model in a simulation environment is disclosed, wherein the processor simulation model includes at least one execution unit for executing at least one instruction of a test file. The method includes tracking each execution of each of the at least one instruction, monitoring relevant signals in each simulation cycle, maintaining information about the execution of the at least one instruction, wherein the maintained information includes a determination of an execution length of a completely executed instruction, matching the maintained information about the completely executed instruction against a set of trap elements provided by the user through a trap file, and collecting the maintained information about the completely executed instruction in a monitor file in response to a match found between the maintained information and at least one of the trap elements.
摘要翻译：公开了一种使用仿真环境中的处理器仿真模型验证处理器设计的改进方法，其中所述处理器仿真模型包括用于执行测试文件的至少一个指令的至少一个执行单元。该方法包括跟踪每个执行至少一个指令中的每一个，监视每个模拟周期中的相关信号，维护关于至少一个指令的执行的信息，其中维护的信息包括完全执行的执行长度的确定指令，将关于完全执行的指令的维护信息与由用户通过陷阱文件提供的一组陷阱元素相匹配，并且响应于在维护信息之间找到的匹配而将关于完全执行的指令的维护信息收集在监视文件中和至少一个捕获元件。

5. 发明申请

US20090063829A1 Method, System, computer program product and data processing program for verifying a processor Design 有权
标题翻译：方法，系统，计算机程序产品和数据处理程序，用于验证处理器设计
公开(公告)号：US20090063829A1
公开(公告)日：2009-03-05
申请号：US12182211
申请日：2008-07-30
申请人： Stefan Letz , Kai Weber , Juergen Vielfort
发明人： Stefan Letz , Kai Weber , Juergen Vielfort
IPC分类号： G06F9/30
CPC分类号： G06F9/3859 , G06F17/5022 , G06F2217/68
摘要： An improved method of verifying a processor design using a processor simulation model in a simulation environment is disclosed, wherein the processor simulation model comprises at least one execution unit for executing at least one instruction of a test file. The method comprises tracking each execution of each of the at least one instruction, monitoring relevant signals in each simulation cycle, maintaining information about the execution of the at least one instruction, wherein said maintained information comprises a determination of an execution length of a completely executed instruction, matching said maintained information about said completely executed instruction against a set of trap elements provided by the user through a trap file, and collecting the maintained information about the completely executed instruction in a monitor file in response to a match found between the maintained information and at least one of the trap elements.
摘要翻译：公开了一种使用仿真环境中的处理器仿真模型验证处理器设计的改进方法，其中所述处理器仿真模型包括用于执行测试文件的至少一个指令的至少一个执行单元。该方法包括跟踪每个执行至少一个指令中的每一个，监视每个模拟周期中的相关信号，维护关于至少一个指令的执行的信息，其中所述维护的信息包括确定完全执行的执行长度指令，将关于所述完全执行的指令的所述维护信息与由用户通过陷阱文件提供的一组陷阱元素进行匹配，以及响应于在所述维护信息之间找到的匹配而将关于完全执行的指令的维护信息收集在监视文件中和至少一个捕获元件。

6. 发明申请

US20120284007A1 VERIFYING A PROCESSOR DESIGN USING A PROCESSOR SIMULATION MODEL 失效
标题翻译：使用处理器模拟模型验证处理器设计
公开(公告)号：US20120284007A1
公开(公告)日：2012-11-08
申请号：US13552634
申请日：2012-07-18
申请人： Stefan Letz , Kai Weber , Juergen Vielfort
发明人： Stefan Letz , Kai Weber , Juergen Vielfort
IPC分类号： G06F17/50
CPC分类号： G06F9/3859 , G06F17/5022 , G06F2217/68
摘要： An improved method of verifying a processor design using a processor simulation model in a simulation environment is disclosed, wherein the processor simulation model includes at least one execution unit for executing at least one instruction of a test file. The method includes tracking each execution of each of the at least one instruction, monitoring relevant signals in each simulation cycle, maintaining information about the execution of the at least one instruction, wherein the maintained information includes a determination of an execution length of a completely executed instruction, matching the maintained information about the completely executed instruction against a set of trap elements provided by the user through a trap file, and collecting the maintained information about the completely executed instruction in a monitor file in response to a match found between the maintained information and at least one of the trap elements.
摘要翻译：公开了一种使用仿真环境中的处理器仿真模型验证处理器设计的改进方法，其中所述处理器仿真模型包括用于执行测试文件的至少一个指令的至少一个执行单元。该方法包括跟踪每个执行至少一个指令中的每一个，监视每个模拟周期中的相关信号，维护关于至少一个指令的执行的信息，其中维护的信息包括完全执行的执行长度的确定指令，将关于完全执行的指令的维护信息与由用户通过陷阱文件提供的一组陷阱元素相匹配，并且响应于在维护信息之间找到的匹配而将关于完全执行的指令的维护信息收集在监视文件中和至少一个捕获元件。

7. 发明授权

US07865793B2 Test case generation with backward propagation of predefined results and operand dependencies 有权
标题翻译：具有预定义结果和操作数依赖性的反向传播的测试用例生成
公开(公告)号：US07865793B2
公开(公告)日：2011-01-04
申请号：US12113116
申请日：2008-04-30
申请人： Stefan Letz , Juergen Vielfort , Kai Weber
发明人： Stefan Letz , Juergen Vielfort , Kai Weber
IPC分类号： G01R31/28 , G06F11/00 , G06F7/38 , G06F9/44
CPC分类号： G06F11/3688
摘要： A method of generating a test case from a given test case structure, the method including generating instructions for the given test case structure, propagating predefined results in a backwards manner, randomly generating remaining operands of the test case structure in a forwards manner, and calculating a result for the test case by determining missing input operands and storing these input operands in both the temporary register file and the initial register file, and calculating missing results and storing all results in the temporary register file.
摘要翻译：一种从给定的测试用例结构生成测试用例的方法，该方法包括生成给定的测试用例结构的指令，以向后的方式传播预定义的结果，以向前的方式随机生成测试用例结构的剩余操作数，以及计算通过确定缺少的输入操作数并将这些输入操作数存储在临时寄存器文件和初始寄存器文件中，并计算缺失的结果并将所有结果存储在临时寄存器文件中，这是测试用例的结果。

8. 发明授权

US09015025B2 Verifying processor-sparing functionality in a simulation environment 有权
公开(公告)号：US09015025B2
公开(公告)日：2015-04-21
申请号：US13285460
申请日：2011-10-31
申请人： Stefan Letz , Joerg Deutschle , Bodo Hoppe , Erica Stuecheli , Brian W. Thompto
发明人： Stefan Letz , Joerg Deutschle , Bodo Hoppe , Erica Stuecheli , Brian W. Thompto
IPC分类号： G06F17/50 , G06F11/22 , G06F11/20
CPC分类号： G06F17/5009 , G06F11/202 , G06F11/2242 , G06F17/5022 , G06F2217/68
摘要： A simulation environment verifies processor-sparing functions in a simulated processor core. The simulation environment executes a first simulation for a simulated processor core. During the simulation, the simulation environment creates a simulation model dump file. At a later point in time, the simulation environment executes a second simulation for the simulated processor core. The simulation environment saves the state of the simulated processor core. The simulation environment then replaces the state of the simulated processor core by loading the previously created simulation model dump file. The simulation environment then sets the state of the simulated processor core to execute processor-sparing code and resumes the second simulation.

9. 发明授权

US08527749B2 User device, computer program product and computer system for system for secure network storage 失效
标题翻译：用户设备，计算机程序产品和用于安全网络存储系统的计算机系统
公开(公告)号：US08527749B2
公开(公告)日：2013-09-03
申请号：US12944058
申请日：2010-11-11
申请人： Oliver Augenstein , Stefan Letz
发明人： Oliver Augenstein , Stefan Letz
IPC分类号： H04L29/06
CPC分类号： G06F3/0605 , G06F3/0665 , G06F3/067 , G06F21/6272
摘要： A technique for providing secure network storage by a user device that includes one or multiple network interfaces, a driver configuration component comprising a volume mapping schema and a connection mapping schema, and a driver operable to map I/O requests for logical data blocks to one or multiple network storage volumes as specified by the volume mapping schema, the data transfer between the user device and the one or multiple network storage volumes being mapped to one or multiple network connections as specified by the connection mapping schema, the driver thereby being operable to provide the user device with a logical storage volume.
摘要翻译：一种用于由包括一个或多个网络接口的用户设备提供安全网络存储的技术，包括卷映射模式和连接映射模式的驱动器配置组件，以及用于将逻辑数据块的I / O请求映射到一个或由卷映射模式指定的多个网络存储卷，用户设备和一个或多个网络存储卷之间的数据传输被映射到由连接映射模式指定的一个或多个网络连接，因此驱动器可操作以向用户设备提供逻辑存储卷。

10. 发明授权

US08001212B2 Method and data processing system for providing XML data 失效
标题翻译：提供XML数据的方法和数据处理系统
公开(公告)号：US08001212B2
公开(公告)日：2011-08-16
申请号：US12109518
申请日：2008-04-25
申请人： Stefan Letz , Roland Seiffert
发明人： Stefan Letz , Roland Seiffert
IPC分类号： G06F15/16
CPC分类号： G06F17/30938 , H04L29/08846 , H04L67/28
摘要： A method and systems for providing XML data is disclosed. In accordance with an embodiment of the invention, a second data processing system, which is connected to a first data processing system via a network, receives a first request over the network from the first data processing system. The first request comprises specifications for subsequent transfers of XML data from the second data processing system to the first data processing system. The specifications specify for which type of XML documents to be transferred in subsequent transfers to the first data processing system which excerpts of XML data shall be sent. An acknowledge message, sent to the first data processing system from the second data processing system, indicates the latter's ability to provide the excerpts of XML data for the types of XML documents in the subsequent data transfers.
摘要翻译：公开了一种用于提供XML数据的方法和系统。根据本发明的实施例，经由网络连接到第一数据处理系统的第二数据处理系统通过网络从第一数据处理系统接收第一请求。第一请求包括用于从第二数据处理系统到第一数据处理系统的XML数据的后续传送的规范。该规范规定在后续传送到要传送的第一个数据处理系统中传送的XML文档类型，将会发送XML数据摘录。从第二个数据处理系统发送到第一个数据处理系统的确认消息指示后者能够在随后的数据传输中提供XML文档的类型的XML数据的摘录。

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