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1. 发明申请

US20120261725A1 Stabilized Metal Silicides in Silicon-Germanium Regions of Transistor Elements 有权
标题翻译：晶体管元素硅锗区稳定金属硅化物
公开(公告)号：US20120261725A1
公开(公告)日：2012-10-18
申请号：US13086516
申请日：2011-04-14
申请人： Stefan Flachowsky , Clemens Fitz , Tom Herrmann
发明人： Stefan Flachowsky , Clemens Fitz , Tom Herrmann
IPC分类号： H01L29/772 , H01L21/265
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/28518 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： Generally, the present disclosure is directed to methods of stabilizing metal silicide contact regions formed in a silicon-germanium active area of a semiconductor device, and devices comprising stabilized metal silicides. One illustrative method disclosed herein includes performing an activation anneal to activate dopants implanted in an active area of a semiconductor device, wherein the active area comprises germanium. Additionally, the method includes, among other things, performing an ion implantation process to implant ions into the active area after performing the activation anneal, forming a metal silicide contact region in the active area, and forming a conductive contact element to the metal silicide contact region.
摘要翻译：通常，本公开涉及稳定在半导体器件的硅 - 锗有源区域中形成的金属硅化物接触区域的稳定化方法，以及包括稳定的金属硅化物的器件。本文公开的一种说明性方法包括执行激活退火以激活植入半导体器件的有源区域中的掺杂剂，其中所述有源区域包括锗。另外，该方法尤其包括执行离子注入工艺以在进行激活退火之后将离子注入到有源区域中，在有源区域中形成金属硅化物接触区域，并在金属硅化物接触部分形成导电接触元件地区。

2. 发明授权

US08859408B2 Stabilized metal silicides in silicon-germanium regions of transistor elements 有权
标题翻译：稳定的金属硅化物在晶体管元件的硅 - 锗区域
公开(公告)号：US08859408B2
公开(公告)日：2014-10-14
申请号：US13086516
申请日：2011-04-14
申请人： Stefan Flachowsky , Clemens Fitz , Tom Herrmann
发明人： Stefan Flachowsky , Clemens Fitz , Tom Herrmann
IPC分类号： H01L21/425 , H01L29/66 , H01L29/165 , H01L21/285 , H01L21/265 , H01L29/78
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/28518 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： Generally, the present disclosure is directed to methods of stabilizing metal silicide contact regions formed in a silicon-germanium active area of a semiconductor device, and devices comprising stabilized metal silicides. One illustrative method disclosed herein includes performing an activation anneal to activate dopants implanted in an active area of a semiconductor device, wherein the active area comprises germanium. Additionally, the method includes, among other things, performing an ion implantation process to implant ions into the active area after performing the activation anneal, forming a metal silicide contact region in the active area, and forming a conductive contact element to the metal silicide contact region.
摘要翻译：通常，本公开涉及稳定在半导体器件的硅 - 锗有源区域中形成的金属硅化物接触区域的稳定化方法，以及包括稳定的金属硅化物的器件。本文公开的一种说明性方法包括执行激活退火以激活植入半导体器件的有源区域中的掺杂剂，其中所述有源区域包括锗。另外，该方法尤其包括执行离子注入工艺以在进行激活退火之后将离子注入到有源区域中，在有源区域中形成金属硅化物接触区域，并在金属硅化物接触部分形成导电接触元件地区。

3. 发明申请

US20130052819A1 Methods of Forming Metal Silicide Regions on Semiconductor Devices Using Different Temperatures 有权
标题翻译：在使用不同温度的半导体器件上形成金属硅化物区域的方法
公开(公告)号：US20130052819A1
公开(公告)日：2013-02-28
申请号：US13218089
申请日：2011-08-25
申请人： Thilo Scheiper , Peter Javorka , Stefan Flachowsky , Clemens Fitz
发明人： Thilo Scheiper , Peter Javorka , Stefan Flachowsky , Clemens Fitz
IPC分类号： H01L21/3205
CPC分类号： H01L21/28518 , H01L21/823814 , H01L21/823835
摘要： Disclosed herein are various methods of forming metal silicide regions on semiconductor devices by using different temperatures during the silicidation processes. In one example, the method includes forming a plurality of N-doped source/drain regions and a plurality of P-doped source/drain regions in a semiconducting substrate and performing a first heating process at a first temperature to initially form a first metal silicide region in each of the P-doped source/drain regions. The method further includes performing a second heating process at a second temperature to initially form a second metal silicide region in each of the N-doped source/drain regions, wherein the second temperature is less than the first temperature and performing a third heating process at a third temperature to complete the formation of the first and second metal silicide regions, wherein the third temperature is greater than the first temperature.
摘要翻译：本文公开了通过在硅化工艺期间使用不同温度在半导体器件上形成金属硅化物区域的各种方法。在一个示例中，该方法包括在半导体衬底中形成多个N掺杂源极/漏极区域和多个P掺杂的源极/漏极区域，并且在第一温度下执行第一加热过程以最初形成第一金属硅化物每个P掺杂源/漏区中的区域。该方法还包括在第二温度下执行第二加热处理，以在N掺杂源极/漏极区域中的每一个中初始形成第二金属硅化物区域，其中第二温度小于第一温度，并且在第三温度以完成所述第一和第二金属硅化物区域的形成，其中所述第三温度大于所述第一温度。

4. 发明授权

US08815736B2 Methods of forming metal silicide regions on semiconductor devices using different temperatures 有权
标题翻译：在使用不同温度的半导体器件上形成金属硅化物区域的方法
公开(公告)号：US08815736B2
公开(公告)日：2014-08-26
申请号：US13218089
申请日：2011-08-25
申请人： Thilo Scheiper , Peter Javorka , Stefan Flachowsky , Clemens Fitz
发明人： Thilo Scheiper , Peter Javorka , Stefan Flachowsky , Clemens Fitz
IPC分类号： H01L21/8238 , H01L21/44 , H01L21/285
CPC分类号： H01L21/28518 , H01L21/823814 , H01L21/823835
摘要： Disclosed herein are various methods of forming metal silicide regions on semiconductor devices by using different temperatures during the silicidation processes. In one example, the method includes forming a plurality of N-doped source/drain regions and a plurality of P-doped source/drain regions in a semiconducting substrate and performing a first heating process at a first temperature to initially form a first metal silicide region in each of the P-doped source/drain regions. The method further includes performing a second heating process at a second temperature to initially form a second metal silicide region in each of the N-doped source/drain regions, wherein the second temperature is less than the first temperature and performing a third heating process at a third temperature to complete the formation of the first and second metal silicide regions, wherein the third temperature is greater than the first temperature.
摘要翻译：本文公开了通过在硅化工艺期间使用不同温度在半导体器件上形成金属硅化物区域的各种方法。在一个示例中，该方法包括在半导体衬底中形成多个N掺杂源极/漏极区域和多个P掺杂的源极/漏极区域，并且在第一温度下执行第一加热过程以最初形成第一金属硅化物每个P掺杂源/漏区中的区域。该方法还包括在第二温度下执行第二加热处理，以在N掺杂源极/漏极区域中的每一个中初始形成第二金属硅化物区域，其中第二温度小于第一温度，并且在第三温度以完成所述第一和第二金属硅化物区域的形成，其中所述第三温度大于所述第一温度。

5. 发明申请

US20130049124A1 MOSFET INTEGRATED CIRCUIT WITH IMPROVED SILICIDE THICKNESS UNIFORMITY AND METHODS FOR ITS MANUFACTURE 审中-公开
标题翻译：具有改进的硅酸盐厚度均匀的MOSFET集成电路及其制造方法
公开(公告)号：US20130049124A1
公开(公告)日：2013-02-28
申请号：US13223016
申请日：2011-08-31
申请人： Clemens Fitz , Stephan Waidmann , Stefan Flachowsky , Peter Baars , Rainer Giedigkeit
发明人： Clemens Fitz , Stephan Waidmann , Stefan Flachowsky , Peter Baars , Rainer Giedigkeit
IPC分类号： H01L27/088 , H01L21/3205
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/823425 , H01L29/1083 , H01L29/165 , H01L29/6659 , H01L29/7848
摘要： An MOSFET device having a Silicide layer of uniform thickness and which is substantially free of “Spotty” NiSi-type holes, and methods for its fabrication, are provided. One such method involves simultaneously depositing a metal layer (e.g. Ni) over the active and open areas of a semiconductor substrate. The depth to which some or all of the metal is transferred into the substrate is determined by thermal budget. A rapid thermal annealing process is employed to produce a NiSi layer of a uniform thickness in both the active and open areas. Upon achieving a NiSi layer of a desired thickness, the excess metal is removed from the substrate surface.
摘要翻译：具有均匀厚度并且基本上没有斑点NiSi型孔的硅化物层的MOSFET器件及其制造方法。一种这样的方法涉及在半导体衬底的有源和开放区域上同时沉积金属层（例如Ni）。一些或全部金属转移到基底中的深度由热预算确定。采用快速热退火工艺来在活性和开放区域中制备均匀厚度的NiSi层。在达到所需厚度的NiSi层时，从衬底表面去除多余的金属。

6. 发明申请

US20130058559A1 METHOD AND APPARATUS FOR CHARACTERIZING DISCONTINUITIES IN SEMICONDUCTOR DEVICES 有权
标题翻译：用于表征半导体器件中不连续性的方法和装置
公开(公告)号：US20130058559A1
公开(公告)日：2013-03-07
申请号：US13223998
申请日：2011-09-01
申请人： Jochen Rinderknecht , Inka Richter , Clemens Fitz
发明人： Jochen Rinderknecht , Inka Richter , Clemens Fitz
IPC分类号： G06K9/00
CPC分类号： G06T7/0006 , G06T2207/10061 , G06T2207/30148
摘要： An approach is provided for characterizing discontinuities in semiconductor devices, for example in a metal silicide. An image of an integrated circuit is caused, at least in part, to be received. The image is analyzed for at least one discontinuity in the integrated circuit structure. A relative measure of the at least one discontinuity is determined in comparison to the integrated circuit structure based on analyzing the image.
摘要翻译：提供了用于表征半导体器件中的不连续性的方法，例如在金属硅化物中。至少部分地引起集成电路的图像被接收。分析图像在集成电路结构中的至少一个不连续性。与基于分析图像的集成电路结构相比，确定至少一个不连续性的相对度量。

7. 发明申请

US20120220086A1 METHODS FOR FABRICATING A CMOS INTEGRATED CIRCUIT HAVING A DUAL STRESS LAYER (DSL) 有权
标题翻译：用于制造具有双应力层（DSL）的CMOS集成电路的方法
公开(公告)号：US20120220086A1
公开(公告)日：2012-08-30
申请号：US13034902
申请日：2011-02-25
申请人： Peter Baars , Marco Lepper , Clemens Fitz
发明人： Peter Baars , Marco Lepper , Clemens Fitz
IPC分类号： H01L21/8238 , H01L21/30
CPC分类号： H01L21/823807 , H01L21/3105 , H01L21/823814 , H01L21/823864
摘要： Methods are provided for fabricating a CMOS integrated circuit having a dual stress layer without NiSi hole formation. One method includes depositing a tensile stress layer overlying a semiconductor substrate. A portion of the tensile stress layer is removed, leaving a remaining portion, before applying a curing radiation. A curing radiation is then applied to the remaining portion; and a compressive stress layer is deposited overlying the semiconductor substrate and the remaining portion.
摘要翻译：提供了用于制造具有不具有NiSi孔形成的双应力层的CMOS集成电路的方法。一种方法包括沉积覆盖半导体衬底的拉伸应力层。在施加固化辐射之前，去除一部分拉伸应力层，留下剩余部分。然后将固化辐射施加到剩余部分; 并且沉积覆盖半导体衬底和剩余部分的压应力层。

8. 发明授权

US08008729B2 Integrated circuit with a contact structure including a portion arranged in a cavity of a semiconductor structure 有权
标题翻译：具有包括布置在半导体结构的空腔中的部分的接触结构的集成电路
公开(公告)号：US08008729B2
公开(公告)日：2011-08-30
申请号：US12251864
申请日：2008-10-15
申请人： Werner Graf , Clemens Fitz
发明人： Werner Graf , Clemens Fitz
IPC分类号： H01L23/522
CPC分类号： H01L21/743 , H01L21/823418 , H01L21/823475 , H01L23/485 , H01L29/66636 , H01L2221/1063 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a contact structure with a buried first and a protruding second portion. The buried first portion is arranged in a cavity formed in a semiconductor structure and is in direct contact with the semiconductor structure. The protruding second portion is arranged above the main surface of the semiconductor structure and in direct contact with a conductive structure that is spaced apart from or separated from the main surface of the semiconductor structure. An insulator structure is arranged below and in direct contact with the contact structure.
摘要翻译：集成电路包括具有埋入的第一和突出的第二部分的接触结构。掩埋的第一部分布置在形成于半导体结构中并与半导体结构直接接触的空腔中。突出的第二部分布置在半导体结构的主表面上方，并且与与半导体结构的主表面间隔开或分离的导电结构直接接触。绝缘体结构布置在接触结构的下方并直接接触。

9. 发明申请

US20130234213A1 NISI REWORK PROCEDURE TO REMOVE PLATINUM RESIDUALS 有权
标题翻译： NISI淘汰淘汰计划废除残留物
公开(公告)号：US20130234213A1
公开(公告)日：2013-09-12
申请号：US13415492
申请日：2012-03-08
申请人： Sivakumar KUMARASAMY , Clemens Fitz , Markus Lenski , Jochen Poth , Kristin Schupke
发明人： Sivakumar KUMARASAMY , Clemens Fitz , Markus Lenski , Jochen Poth , Kristin Schupke
IPC分类号： H01L21/66 , H01L29/68
CPC分类号： H01L21/28518 , H01L22/12 , H01L22/20
摘要： The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing a rework including applying SPM at a temperature of 130° C. in a SWC tool, if Pt residue is detected. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer, annealing the Ni removed Ni/Pt layer, removing unreacted Pt from the annealed Ni removed Ni/Pt layer, analyzing the Pt removed Ni/Pt layer for unreacted Pt residue, and if unreacted Pt residue is detected, applying SPM to the Pt removed Ni/Pt layer in a SWC tool. The SPM may be applied to the Pt removed Ni'/Pt layer at a temperature of 130° C.
摘要翻译：如果检测到Pt残留物，则通过执行包括在SWC工具中在130℃的温度下施加SPM的返工来减少形成含Pt的NiSi后剩余的Pt残余物的量。实施例包括在半导体衬底上沉积一层Ni / Pt，退火沉积的Ni / Pt层，从退火的Ni / Pt层去除未反应的Ni，退火Ni去除的Ni / Pt层，从退火的Ni中除去未反应的Pt Ni / Pt层，分析未去除Pt残留物的Pt去除Ni / Pt层，如果检测到未反应的Pt残留物，则在SWC工具中将Pt施加到去除的Pt / Ni层上。可以在130℃的温度下将SPM施加到Pt去除的Ni'/ Pt层上

10. 发明授权

US08293605B2 Methods for fabricating a CMOS integrated circuit having a dual stress layer (DSL) 有权
标题翻译：制造具有双重应力层（DSL）的CMOS集成电路的方法
公开(公告)号：US08293605B2
公开(公告)日：2012-10-23
申请号：US13034902
申请日：2011-02-25
申请人： Peter Baars , Marco Lepper , Clemens Fitz
发明人： Peter Baars , Marco Lepper , Clemens Fitz
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/3105 , H01L21/823814 , H01L21/823864
摘要： Methods are provided for fabricating a CMOS integrated circuit having a dual stress layer without NiSi hole formation. One method includes depositing a tensile stress layer overlying a semiconductor substrate. A portion of the tensile stress layer is removed, leaving a remaining portion, before applying a curing radiation. A curing radiation is then applied to the remaining portion; and a compressive stress layer is deposited overlying the semiconductor substrate and the remaining portion.
摘要翻译：提供了用于制造具有不具有NiSi孔形成的双应力层的CMOS集成电路的方法。一种方法包括沉积覆盖半导体衬底的拉伸应力层。在施加固化辐射之前，去除一部分拉伸应力层，留下剩余部分。然后将固化辐射施加到剩余部分; 并且沉积覆盖半导体衬底和剩余部分的压应力层。

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