专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06542389B2 Voltage pump with switch-on control 失效
公开(公告)号：US06542389B2
公开(公告)日：2003-04-01
申请号：US10046378
申请日：2001-10-19
申请人： Stefan Dietrich , Patrick Heyne , Thilo Marx , Sabine Kieser , Michael Sommer , Thomas Hein , Michael Markert , Torsten Partsch , Peter Schrögmeier , Christian Weis
发明人： Stefan Dietrich , Patrick Heyne , Thilo Marx , Sabine Kieser , Michael Sommer , Thomas Hein , Michael Markert , Torsten Partsch , Peter Schrögmeier , Christian Weis
IPC分类号： H02M307
CPC分类号： H02M3/07
摘要： The voltage pump for generating a boosted output voltage has a switch-on control circuit. The switch-on control includes a transistor that is connected between a terminal for feeding in a supply voltage and the terminal for tapping off the boosted output voltage. After the voltage pump has started to operate, the boosted output voltage is decoupled from the supply voltage by the transistor. A changeover switch forwards the respective higher of the output voltage or supply voltage to the substrate terminal and gate terminal of the transistor. The switch-on control enables early provision of a boosted output voltage in conjunction with reliable start-up operation of the voltage pump, while the additional outlay on circuitry is minimized.

2. 发明授权

US06670802B2 Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits 有权
公开(公告)号：US06670802B2
公开(公告)日：2003-12-30
申请号：US10033131
申请日：2001-10-22
申请人： Stefan Dietrich , Patrick Heyne , Thilo Marx , Sabine Kieser , Michael Sommer , Thomas Hein , Michael Markert , Torsten Partsch , Peter Schroegmeier , Christian Weis
发明人： Stefan Dietrich , Patrick Heyne , Thilo Marx , Sabine Kieser , Michael Sommer , Thomas Hein , Michael Markert , Torsten Partsch , Peter Schroegmeier , Christian Weis
IPC分类号： G01R3102
CPC分类号： G11C29/003
摘要： Integrated circuits, in particular memory chips of the DDR SDRAM type, are tested in a parallel manner. In order to prevent the circuits from being driven relative to one another during a test operation, an input terminal that is already connected to a channel of an automatic test machine anyway is connected to a switching device, by which the output drivers can be turned off in a manner dependent on the control signal that can be fed in at the input terminal. The switching device preferably contains a demultiplexer and also a multiplexer. The demultiplexer can be driven by a test control signal that is additionally generated besides the test control signal. The input terminal is connected to a tester channel anyway during test operation, with the result that no additional external outlay arises.

3. 发明授权

US06480024B2 Circuit configuration for programming a delay in a signal path 有权
公开(公告)号：US06480024B2
公开(公告)日：2002-11-12
申请号：US10046395
申请日：2001-10-19
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Michael Markert , Thilo Marx , Torsten Partsch , Sabine Schöniger Kieser , Peter Schrögmeier , Michael Sommer , Christian Weis
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Michael Markert , Thilo Marx , Torsten Partsch , Sabine Schöniger Kieser , Peter Schrögmeier , Michael Sommer , Christian Weis
IPC分类号： H03K190173
CPC分类号： H03K5/133 , H03K2005/00065 , H03K2005/00071 , H03K2005/00091
摘要： A circuit configuration includes two signal path sections that are used to program the delay of a signal path, in particular in DRAMs. The two signal path sections have different delays and can be driven in parallel at the input end. The two signal path sections can be connected to an output terminal via a multiplexer. A selection circuit includes two signal path sections which are connected between supply voltage potentials. The selection circuit has two complimentary transistors which are connected in series and has source-end programmable elements. These transistors can be driven by complimentary control signals. This permits the delay to be programmed flexibly with little expenditure on circuitry.

4. 发明授权

US06532188B2 Integrated memory having a row access controller for activating and deactivating row lines 有权
公开(公告)号：US06532188B2
公开(公告)日：2003-03-11
申请号：US10012161
申请日：2001-10-29
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Thilo Marx , Torsten Partsch , Sabine Kieser , Peter Schroegmeier , Michael Sommer , Christian Weis
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Thilo Marx , Torsten Partsch , Sabine Kieser , Peter Schroegmeier , Michael Sommer , Christian Weis
IPC分类号： G11C800
CPC分类号： G11C8/08 , G11C8/10 , G11C8/18
摘要： An integrated memory is described which has a memory cell array with column lines and row lines. A row access controller serves for activating one of the row lines and for controlling a deactivation operation. An input of a control unit is connected to a signal terminal for a signal that, in the event of a read access to one of the memory cells, defines the beginning of data outputting to a point outside the memory cell array. The data output is synchronized with a clock signal. In this case, the signal is adjustable depending on an operating frequency of the memory. An output signal of the control unit serves for triggering the deactivation operation of one of the row lines after a write access. Therefore, in the event of a write access, a comparatively high data throughput is possible even at different operating frequencies of the integrated memory.

5. 发明授权

US06388944B2 Memory component with short access time 有权
标题翻译：具有访问时间短的内存组件
公开(公告)号：US06388944B2
公开(公告)日：2002-05-14
申请号：US09773221
申请日：2001-01-31
申请人： Peter Schrögmeier , Stefan Dietrich , Torsten Partsch , Thomas Hein , Patrick Heyne , Thilo Marx
发明人： Peter Schrögmeier , Stefan Dietrich , Torsten Partsch , Thomas Hein , Patrick Heyne , Thilo Marx
IPC分类号： G11C800
CPC分类号： G11C7/1069
摘要： A memory chip with a short data access time limits the propagation time of a bit on local data line strips which are far away from output amplifiers by centering switches with respect to a center of the cell array strips, wherein the switches are junction points between local data lines and main data lines.
摘要翻译：具有短数据访问时间的存储器芯片通过相对于单元阵列条的中心对中开关来限制远离输出放大器的本地数据线条上的位的传播时间，其中开关是本地数据线和主数据线。

6. 发明授权

US07016452B2 Delay locked loop 有权
公开(公告)号：US07016452B2
公开(公告)日：2006-03-21
申请号：US10178249
申请日：2002-06-24
申请人： Torsten Partsch , Thomas Hein , Thilo Marx , Patrick Heyne
发明人： Torsten Partsch , Thomas Hein , Thilo Marx , Patrick Heyne
IPC分类号： H03D3/24
CPC分类号： H03L7/0814 , H03K5/131 , H03K5/133 , H03K2005/00058
摘要： A delay locked loop includes a delay unit with a controllable delay time. Switching elements are provided in order to tap off output signals from the delay elements of the delay unit. Two nodes connected to the switching elements are connected to a multiplexer configuration in order to activate in each case two of the switching elements that are connected to delay elements connected directly in succession. A phase interpolator generates an intermediate phase from the signals provided.

7. 发明授权

US06285228B1 Integrated circuit for generating a phase-shifted output clock signal from a clock signal 有权
标题翻译：用于从时钟信号产生相移输出时钟信号的集成电路
公开(公告)号：US06285228B1
公开(公告)日：2001-09-04
申请号：US09606594
申请日：2000-06-29
申请人： Patrick Heyne , Thomas Hein , Torsten Partsch , Thilo Marx
发明人： Patrick Heyne , Thomas Hein , Torsten Partsch , Thilo Marx
IPC分类号： H03K500
CPC分类号： H03L7/0805 , H03K5/133 , H03K2005/00019 , H03L7/0814
摘要： The integrated circuit generates an output clock signal with a phase shift relative to a first clock signal. The currents IE=I1 and IL=I2 can be weighted differently by means of control signals. A different phase shift of the output clock signal results depending on the weighting.
摘要翻译：集成电路产生相对于第一时钟信号具有相移的输出时钟信号。通过控制信号可以不同地加权电流IE = I1和IL = I2。输出时钟信号的不同相移取决于加权。

8. 发明授权

US06285176B1 Voltage generator with superimposed reference voltage and deactivation signals 有权
标题翻译：具有叠加参考电压和去激活信号的电压发生器
公开(公告)号：US06285176B1
公开(公告)日：2001-09-04
申请号：US09693778
申请日：2000-10-20
申请人： Thilo Marx , Torsten Partsch , Thomas Hein , Patrick Heyne
发明人： Thilo Marx , Torsten Partsch , Thomas Hein , Patrick Heyne
IPC分类号： G05F316
CPC分类号： G05F1/465
摘要： A voltage generator configuration includes a voltage generator which generates a second voltage from a first voltage using a reference voltage and which can be deactivated by using a deactivation signal. The voltage generator configuration is distinguished in that the deactivation signal is fed to the voltage generator over a line through which the reference voltage is also fed to the voltage generator.
摘要翻译：电压发生器配置包括电压发生器，该电压发生器使用参考电压从第一电压产生第二电压，并且可以通过使用去激活信号来去激活。电压发生器配置的区别在于，去激活信号通过一个线路馈送到电压发生器，通过该线路，参考电压也被馈送到电压发生器。

9. 发明授权

US06259652B1 Synchronous integrated memory 失效
标题翻译：同步集成存储器
公开(公告)号：US06259652B1
公开(公告)日：2001-07-10
申请号：US09624448
申请日：2000-07-24
申请人： Patrick Heyne , Thomas Hein , Torsten Partsch , Thilo Marx
发明人： Patrick Heyne , Thomas Hein , Torsten Partsch , Thilo Marx
IPC分类号： G11C700
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1066
摘要： Data items D1, D2 read from memory cells MC are simultaneously buffer-stored in memory stages Si of a FIFO memory MEM and are read out again simultaneously from said FIFO memory at a later point in time. Output units OC1, OC2 serve for outputting, at a data output P, the first data D1 synchronously with positive edges of an external clock signal CLK and the second data D2 synchronously with negative edges of the external clock signal CLK.
摘要翻译：从存储器单元MC读取的数据项D1，D2同时被缓冲存储在FIFO存储器MEM的存储级Si中，并且在稍后的时间点再次从所述FIFO存储器读出。输出单元OC1，OC2用于在数据输出端P以与外部时钟信号CLK的负沿同步地与外部时钟信号CLK和第二数据D2的正边沿同步地输出第一数据D1。

10. 发明授权

US06661265B2 Delay locked loop for generating complementary clock signals 有权
标题翻译：用于产生互补时钟信号的延迟锁定环
公开(公告)号：US06661265B2
公开(公告)日：2003-12-09
申请号：US10178251
申请日：2002-06-24
申请人： Torsten Partsch , Thilo Marx , Patrick Heyne , Thomas Hein
发明人： Torsten Partsch , Thilo Marx , Patrick Heyne , Thomas Hein
IPC分类号： H03L706
CPC分类号： H03K5/151 , H03K5/133 , H03K2005/00039 , H03K2005/00195 , H03L7/0812
摘要： A delay locked loop has a delay unit with a delay time that can be controlled in a manner dependent on a control signal. In order to generate complementary delayed clock signals, provision is made of switching elements, which tap off the clock signal to be delayed along the series circuit of delay elements. Each of the delay elements has a series circuit of two inverters. One of the delayed clock signals is tapped off in each case at the output of the second of the inverters of the delay elements, and the complementary output signal from the delayed output signals is tapped off at the first of the inverters. What is thus made possible is that, disregarding the frequency of the clock signal to be delayed and the length of the delay time, the complementary delayed clock signals always have the same phase angle with respect to one another.
摘要翻译：延迟锁定环路具有可以以取决于控制信号的方式来控制延迟时间的延迟单元。为了产生互补的延迟时钟信号，提供开关元件，其切断时钟信号以沿着延迟元件的串联电路被延迟。每个延迟元件具有两个逆变器的串联电路。在延迟元件的第二反相器的输出处，在每种情况下，延迟时钟信号中的一个被分接，并且来自延迟的输出信号的互补输出信号在第一逆变器处被分接。因此，如果不考虑要延迟的时钟信号的频率和延迟时间的长度，互补延迟的时钟信号总是相对于彼此具有相同的相位角。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式