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    • 1. 发明授权
    • Clock tree insertion delay independent interface
    • 时钟树插入延迟独立接口
    • US08564337B2
    • 2013-10-22
    • US13022824
    • 2011-02-08
    • Stefan BlockHerbert PreuthenJuergen Dirks
    • Stefan BlockHerbert PreuthenJuergen Dirks
    • H03L7/00
    • H04L7/0337G06F1/06G06F1/08
    • Disclosed herein is a multi-clock interface, an integrated circuit and a module thereof having the multi-clock interface and a library having cells corresponding to the above noted circuitry. In one embodiment the multi-clock interface includes: (1) a multi-clock reset synchronizer configured to receive a first external clock signal and a second external clock signal that is a multiple of the first clock signal, the reset synchronizer configured to synchronize a reset of both the first and second external clock signals and based thereon generate a reset release signal and (2) a multi-phase clock generator configured to receive the reset release signal and the second clock signal, the multi-phase clock generator configured to generate multiple clock phases from the second clock signal based on the reset release signal.
    • 这里公开了具有多时钟接口的多时钟接口,集成电路及其模块,以及具有与上述电路对应的单元的库。 在一个实施例中,多时钟接口包括:(1)多时钟复位同步器,被配置为接收第一外部时钟信号和作为第一时钟信号的倍数的第二外部时钟信号,复位同步器被配置为使 复位第一外部时钟信号和第二外部时钟信号,并且基于其产生复位释放信号;以及(2)被配置为接收复位释放信号和第二时钟信号的多相时钟发生器,所述多相时钟发生器被配置为产生 基于复位释放信号的第二时钟信号的多个时钟相位。
    • 2. 发明申请
    • CLOCK TREE INSERTION DELAY INDEPENDENT INTERFACE
    • 时钟插入延迟独立接口
    • US20120200322A1
    • 2012-08-09
    • US13022824
    • 2011-02-08
    • Stefan BlockHerbert PreuthenJuergen Dirks
    • Stefan BlockHerbert PreuthenJuergen Dirks
    • H03L7/00
    • H04L7/0337G06F1/06G06F1/08
    • Disclosed herein is a multi-clock interface, an integrated circuit and a module thereof having the multi-clock interface and a library having cells corresponding to the above noted circuitry. In one embodiment the multi-clock interface includes: (1) a multi-clock reset synchronizer configured to receive a first external clock signal and a second external clock signal that is a multiple of the first clock signal, the reset synchronizer configured to synchronize a reset of both the first and second external clock signals and based thereon generate a reset release signal and (2) a multi-phase clock generator configured to receive the reset release signal and the second clock signal, the multi-phase clock generator configured to generate multiple clock phases from the second clock signal based on the reset release signal.
    • 这里公开了具有多时钟接口的多时钟接口,集成电路及其模块,以及具有与上述电路对应的单元的库。 在一个实施例中,多时钟接口包括:(1)多时钟复位同步器,被配置为接收第一外部时钟信号和作为第一时钟信号的倍数的第二外部时钟信号,复位同步器被配置为使 复位第一外部时钟信号和第二外部时钟信号,并且基于其产生复位释放信号;以及(2)被配置为接收复位释放信号和第二时钟信号的多相时钟发生器,所述多相时钟发生器被配置为产生 基于复位释放信号的第二时钟信号的多个时钟相位。
    • 6. 发明授权
    • Method of providing clock signals to load circuits in an ASIC device
    • 向ASIC设备中的负载电路提供时钟信号的方法
    • US06313683B1
    • 2001-11-06
    • US09301278
    • 1999-04-28
    • Stefan BlockBernd AhnerDavid ReuveniBenjamin Mbouombouo
    • Stefan BlockBernd AhnerDavid ReuveniBenjamin Mbouombouo
    • G06F104
    • G01R31/30G06F1/06G06F1/10
    • An ASIC device and method provide clock signals to load circuits having a balanced clock tree including a master clock line, for example a clock trunk or H-tree, and branched clock lines feeding the clock signals to load circuits and being balanced with respect to the delays and loads in domains of the ASIC device to which the branched clock lines supply the clock signals. The ASIC device and method generate derived clock signals by gating the master clock signal, in which the derived clock signals have a frequency reduced by a factor n>1 (n=2, . . . , N), which is adapted to the need of the load circuits in a particular domain, and route the master clock signal and/or the derived clock signal for a particular domain to the load circuit of said domain.
    • ASIC设备和方法向具有包括主时钟线(例如时钟中继线或H树)的平衡时钟树的负载电路提供时钟信号,以及将时钟信号馈送到负载电路并且相对于 分支时钟线提供时钟信号的ASIC器件的域中的延迟和负载。 ASIC器件和方法通过门控主时钟信号来产生导出的时钟信号,其中导出的时钟信号具有被减少了因子n> 1(n = 2,...,N)的频率,其适应于需要 的特定域中的负载电路,并将主时钟信号和/或用于特定域的导出时钟信号路由到所述域的负载电路。