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1. 发明授权

US08486514B2 Method to fabricate a mould for lithography by nano-imprinting 有权
标题翻译：通过纳米压印制造光刻模具的方法
公开(公告)号：US08486514B2
公开(公告)日：2013-07-16
申请号：US12715738
申请日：2010-03-02
申请人： Stéfan Landis , Yves Morand
发明人： Stéfan Landis , Yves Morand
IPC分类号： B32B3/28 , B32B3/30
CPC分类号： G03F7/0002 , B29C33/42 , B82Y10/00 , B82Y40/00 , G03F7/0017 , Y10T428/24479 , Y10T428/2457 , Y10T428/24744
摘要： A nano-imprint device including at least: a substrate, having a surface, on the substrate, a plurality of nano-trenches parallel two by two, each nano-trench extending in a longitudinal direction and being delimited laterally by side walls, the nano-trenches and the side walls being directed substantially perpendicular to the surface of the substrate, each nano-trench comprising a bottom surface with at least one first and one second level in a direction perpendicular to the substrate, respectively of depth h1 and h2>h1, measured relative to the top of the side walls, and the bottom surfaces of the nano-trenches, of the least deep level (h1) being in a first type of material, the side walls being in a second type of material.
摘要翻译：一种纳米压印装置，其至少包括：在所述基板上具有平行两个的多个纳米沟槽的表面的基板，每个纳米沟槽在纵向方向上延伸并由侧壁横向限定，所述纳米沟槽三角形并且所述侧壁基本上垂直于所述衬底的表面定向，每个纳米沟槽包括底面，所述底表面在垂直于所述衬底的方向上具有至少一个第一和第二水平面，所述方向分别具有深度h1和h2> h1 （h1）处于第一类型的材料中，相对于侧壁的顶部和纳米沟槽的底表面测量的最小深度（h1）的底表面是第二类型的材料。

2. 发明申请

US20090203203A1 METHOD FOR THE FABRICATION OF A TRANSISTOR GATE THAT INCLUDES THE BREAKDOWN OF A PRECURSOR MATERIAL INTO AT LEAST ONE METALLIC MATERIAL, USING AT LEAST ONE 有权
标题翻译：用于制造晶体管的方法，其包括使用至少一种金属材料的前体材料的破裂
公开(公告)号：US20090203203A1
公开(公告)日：2009-08-13
申请号：US12299038
申请日：2007-05-03
申请人： Thomas Ernst , Stéfan Landis
发明人： Thomas Ernst , Stéfan Landis
IPC分类号： H01L21/283
CPC分类号： C23C16/047 , C23C16/18 , G03F7/0042 , G03F7/0047 , H01L21/32051 , H01L29/42384 , H01L29/42392 , H01L29/66787 , H01L29/78696
摘要： A microelectronic method for the fabrication of a transistor gate using a precursor material that is suitable for being broken down into at least one metallic material after having been exposed to an electron beam. The invention applies in particular to the fabrication of multi-channel transistors, of the FinFET, suspended-channel, ITS or GAA type.
摘要翻译：一种使用前体材料制造晶体管栅极的微电子方法，所述前体材料适于在暴露于电子束之后被分解成至少一种金属材料。本发明特别适用于制造FinFET，悬浮通道，ITS或GAA型的多通道晶体管。

3. 发明授权

US08778195B2 Method to fabricate a mould for lithography by nano-imprinting 有权
标题翻译：通过纳米压印制造光刻模具的方法
公开(公告)号：US08778195B2
公开(公告)日：2014-07-15
申请号：US12715801
申请日：2010-03-02
申请人： Stéfan Landis
发明人： Stéfan Landis
IPC分类号： B44C1/22 , B82Y40/00
CPC分类号： G03F7/2059 , B81C99/009 , B81C2201/0159 , B81C2201/034 , B82Y10/00 , B82Y40/00 , G03F7/0002 , G03F7/0017
摘要： A method to fabricate an imprint mould in three dimensions including at least: a) forming at least one trench, of width W and depth h, in a substrate, thereby forming three surfaces including, a bottom of the at least one trench, sidewalls of the at least one trench, and a remaining surface of the substrate, called top of the substrate; b) forming alternate layers in the at least one trench, each having at least one portion perpendicular to the substrate, in a first material and in a second material which can be selectively etched relative to the first material; and c) selectively etching said portions of the layers perpendicular to the substrate.
摘要翻译：一种在三维中制造压印模具的方法，至少包括：a）在衬底中形成宽度为W和深度为h的至少一个沟槽，从而形成三个表面，包括至少一个沟槽的底部，所述至少一个沟槽和所述衬底的剩余表面称为所述衬底的顶部; b）在所述至少一个沟槽中形成交替层，每个沟槽具有至少一部分垂直于所述衬底的第一材料和第二材料，所述第二材料可相对于所述第一材料选择性地蚀刻; 和c）选择性地刻蚀垂直于衬底的层的所述部分。

4. 发明授权

US08173545B2 Method for the fabrication of a transistor gate using at least one electron beam 有权
标题翻译：使用至少一个电子束制造晶体管栅极的方法
公开(公告)号：US08173545B2
公开(公告)日：2012-05-08
申请号：US12299038
申请日：2007-05-03
申请人： Thomas Ernst , Stéfan Landis
发明人： Thomas Ernst , Stéfan Landis
IPC分类号： H01L21/44
CPC分类号： C23C16/047 , C23C16/18 , G03F7/0042 , G03F7/0047 , H01L21/32051 , H01L29/42384 , H01L29/42392 , H01L29/66787 , H01L29/78696
摘要： A microelectronic method for the fabrication of a transistor gate using a precursor material that is suitable for being broken down into at least one metallic material after having been exposed to an electron beam. The invention applies in particular to the fabrication of multi-channel transistors, of the FinFET, suspended-channel, ITS or GAA type.
摘要翻译：一种使用前体材料制造晶体管栅极的微电子方法，所述前体材料适于在暴露于电子束之后被分解成至少一种金属材料。本发明特别适用于制造FinFET，悬浮通道，ITS或GAA型的多通道晶体管。

5. 发明申请

US20100136724A1 METHOD FOR FABRICATING A NANOSTRUCTURED SUBSTRATE FOR OLED AND METHOD FOR FABRICATING AN OLED 有权
标题翻译：用于制造用于OLED的纳米结构化衬底的方法和用于制造OLED的方法
公开(公告)号：US20100136724A1
公开(公告)日：2010-06-03
申请号：US12624616
申请日：2009-11-24
申请人： Alexandre Mary , Luc Andre , Stéfan Landis
发明人： Alexandre Mary , Luc Andre , Stéfan Landis
IPC分类号： H01L21/00
CPC分类号： H01L51/0001 , H01L51/5262 , H01L51/5275 , H01L51/56 , H01L2251/105
摘要： Method for fabricating a substrate comprising a nanostructured surface for an organic light emitting diode OLED, in which a layer of an organic resin or of a mineral material having a first nanostructuration is prepared by nano-imprint; the organic resin or mineral material is heated to a temperature equal to or higher than its glass transition temperature Tg or its melting point, and the organic resin or the mineral material is maintained at this temperature for a time tR called annealing time, whereby the organic resin or the mineral material flows and the first nanostructuration of the layer of organic resin or of mineral material is modified to produce a second nanostructuration; the organic resin or the mineral material is cooled.
摘要翻译：一种制造衬底的方法，该衬底包括用于有机发光二极管OLED的纳米结构表面，其中通过纳米压印制备有机树脂层或具有第一纳米结构的矿物材料层; 将有机树脂或矿物材料加热到等于或高于其玻璃化转变温度Tg或其熔点的温度，并将有机树脂或矿物材料在该温度下保持称为退火时间的时间tR，由此有机树脂或矿物材料流动，并且有机树脂或矿物材料层的第一纳米结构被修饰以产生第二纳米结构; 有机树脂或矿物材料被冷却。

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