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1. 发明申请

US20110086484A1 BODY TIE TEST STRUCTURE FOR ACCURATE BODY EFFECT MEASUREMENT 有权
标题翻译：身体测试结构，用于精确的身体效应测量
公开(公告)号：US20110086484A1
公开(公告)日：2011-04-14
申请号：US12973377
申请日：2010-12-20
申请人： Sriram MADHAVAN , Qiang CHEN , Darin A. CHAN , Jung-Suk GOO
发明人： Sriram MADHAVAN , Qiang CHEN , Darin A. CHAN , Jung-Suk GOO
IPC分类号： H01L21/336
CPC分类号： H01L29/78615 , H01L22/34
摘要： A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.
摘要翻译：提供了一种身体搭接测试结构及其制造方法。晶体管包括形成在半导体材料层中的主体结合半导体绝缘体（SOI）晶体管，该晶体管包括具有基本恒定的栅极长度L的十字形栅极结构。绝缘阻挡层能够形成间隔区域所述半导体材料层将所述源极和漏极区域与所述主体连接区域分开。具有与本征晶体管主体基本上相同的反转特性的导电沟道通过间隔区将主体连接到本征晶体管本体。

2. 发明申请

US20090101976A1 BODY TIE TEST STRUCTURE FOR ACCURATE BODY EFFECT MEASUREMENT 有权
标题翻译：身体测试结构，用于精确的身体效应测量
公开(公告)号：US20090101976A1
公开(公告)日：2009-04-23
申请号：US11874454
申请日：2007-10-18
申请人： Sriram MADHAVAN , Qiang CHEN , Darin A. CHAN , Jung-Suk GOO
发明人： Sriram MADHAVAN , Qiang CHEN , Darin A. CHAN , Jung-Suk GOO
IPC分类号： H01L27/12 , H01L21/8236
CPC分类号： H01L29/78615 , H01L22/34
摘要： A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.
摘要翻译：提供了一种身体搭接测试结构及其制造方法。晶体管包括形成在半导体材料层中的主体结合半导体绝缘体（SOI）晶体管，该晶体管包括具有基本恒定的栅极长度L的十字形栅极结构。绝缘阻挡层能够形成间隔区域所述半导体材料层将所述源极和漏极区域与所述主体连接区域分开。具有与本征晶体管主体基本上相同的反转特性的导电沟道通过间隔区将主体连接到本征晶体管本体。

3. 发明申请

US20080305613A1 METHOD FOR FABRICATING AN SOI DEFINED SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于制造SOI限定半导体器件的方法
公开(公告)号：US20080305613A1
公开(公告)日：2008-12-11
申请号：US11759411
申请日：2007-06-07
申请人： Mario M. PELELLA , Darin A. CHAN
发明人： Mario M. PELELLA , Darin A. CHAN
IPC分类号： H01L21/762
CPC分类号： H01L21/76275 , H01L21/76283 , H01L21/84
摘要： Methods are provided for fabricating a semiconductor on insulator (SOI) component on a semiconductor layer/insulator/substrate structure. The method includes forming one or more shallow trench isolation (STI) regions extending through the semiconductor layer to the insulator. First and second openings are etched through the STI and the insulator using the remaining SOI material in the semiconductor layer as an etch mask. N— and P-type ions are implanted into the substrate through the openings to form to form N-doped and P-doped regions therein, such as an anode and a cathode of a semiconductor diode structure. The N-doped and P-doped regions are closely spaced and precisely aligned to each other by the SOI material in the semiconductor layer. Electrical contacts are then made to the N-doped and P-doped regions.
摘要翻译：提供了用于在半导体层/绝缘体/衬底结构上制造绝缘体上半导体（SOI）部件的方法。该方法包括形成一个或多个穿过半导体层延伸到绝缘体的浅沟槽隔离（STI）区域。通过STI和绝缘体，使用半导体层中剩余的SOI材料作为蚀刻掩模蚀刻第一和第二开口。通过开口将N型和P型离子注入到衬底中以形成其中的N掺杂和P掺杂区域，例如半导体二极管结构的阳极和阴极。 N掺杂和P掺杂区域通过半导体层中的SOI材料彼此紧密间隔并精确地对准。然后对N掺杂和P掺杂区域进行电接触。

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