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1. 发明授权

US6122693A PCI bus utilization diagnostic monitor 有权
标题翻译： PCI总线利用诊断监视器
公开(公告)号：US6122693A
公开(公告)日：2000-09-19
申请号：US140672
申请日：1998-08-26
申请人： Srinivasa Gutta , Raman Parthasarathy , Walter G. Soto
发明人： Srinivasa Gutta , Raman Parthasarathy , Walter G. Soto
IPC分类号： G06F11/34 , G06F12/06 , H04L7/00 , H04L7/02
CPC分类号： G06F11/349 , G06F12/0646 , H04L7/0278 , G06F2201/88 , H04L7/0004 , H04L7/0025 , H04L7/0029
摘要： The present invention provides a PCI Bus Diagnostic Monitor which eliminates the need to hook up a logic analyzer and manually analyze the data passing on the PCI Bus. The present invention provides an accurate analysis of the PCI Bus master's utilization and/or latency time to acquire the PCI Bus by controlling a 12-bit counter and analyzing count values at appropriate times, e.g., between the time the PCI Bus request is output and the time that the data transfer begins, and the time between when the data transfer begins and when the data transfer ends. The data corresponding to a large number of data transfers may be buffered and analyzed to provide performance statistics relating to the PCI Bus. The analysis can be performed in lightly loaded, typically loaded, and heavily loaded PCI bus situations to fully and accurately test real-world capabilities of new peripherals, particular combinations of peripherals, and statistics relating to customized usage of a host system. The accurate statistics relating to the performance of the PCI Bus will also allow a system designer to assign and/or reassign PCI Bus priorities for various bus agents or peripherals.
摘要翻译：本发明提供了一种PCI总线诊断监视器，其不需要连接逻辑分析器并手动分析在PCI总线上传递的数据。本发明通过控制12位计数器并在适当时间分析计数值（例如在PCI总线请求被输出的时间之间）以及在输出PCI总线请求的时间之间提供对PCI总线主机的使用和/或等待时间的准确分析以获得PCI总线数据传输开始的时间以及数据传输开始与数据传输结束之间的时间。可以缓冲和分析对应于大量数据传输的数据，以提供与PCI总线相关的性能统计。该分析可以在轻载，典型负载和负载较重的PCI总线情况下执行，以完全和准确地测试新外设的实际功能，外围设备的特定组合以及与主机系统的定制使用有关的统计数据。与PCI总线性能相关的准确统计数据还将允许系统设计人员为各种总线代理或外设分配和/或重新分配PCI总线优先级。

2. 发明授权

US06240483B1 System for memory based interrupt queue in a memory of a multiprocessor system 有权
标题翻译：用于多处理器系统存储器中的基于内存的中断队列的系统
公开(公告)号：US06240483B1
公开(公告)日：2001-05-29
申请号：US09140673
申请日：1998-08-26
申请人： Srinivasa Gutta , Walter G. Soto , Raman Parthasarathy
发明人： Srinivasa Gutta , Walter G. Soto , Raman Parthasarathy
IPC分类号： G06F1324
CPC分类号： G06F11/349 , G06F12/0646
摘要： An interrupt mechanism which reduces or eliminates the need for an interrupt status register while at the same time provides suitable information to a host or other processor with respect to the cause and parameters surrounding an interrupt signal. An interrupt queue is maintained in shared memory accessible by both a host and an interrupting agent. The interrupt queue has a capacity or two or more separate interrupt requests, either from a same interrupting agent or from two different interrupting agents. As interrupting agents write to the interrupt queue, an agent current interrupt pointer (ACIP) is incremented to a next position in the interrupt queue. As the host services interrupts, the current host pointer is incremented to clear the serviced interrupt request entry.
摘要翻译：一种减少或消除对中断状态寄存器的需求的中断机制，同时相对于围绕中断信号的原因和参数向主机或其他处理器提供合适的信息。在主机和中断代理可访问的共享内存中维护一个中断队列。中断队列具有来自相同中断代理或两个不同中断代理的容量或两个或多个单独的中断请求。当中断代理写入中断队列时，代理当前中断指针（ACIP）递增到中断队列中的下一个位置。当主机服务中断时，当前主机指针被递增，以清除服务中断请求条目。

3. 发明授权

US06965974B1 Dynamic partitioning of memory banks among multiple agents 失效
标题翻译：内存库在多个代理之间进行动态分区
公开(公告)号：US06965974B1
公开(公告)日：2005-11-15
申请号：US09120126
申请日：1998-07-22
申请人： Laurence Edward Bays , Jalil Fadavi-Ardekani , Srinivasa Gutta , Bahram Ghaffarzadeh Kermani , Richard Joseph Niescier , Geoffrey Lawrence Smith , Walter G. Soto , Daniel K. Greenwood
发明人： Laurence Edward Bays , Jalil Fadavi-Ardekani , Srinivasa Gutta , Bahram Ghaffarzadeh Kermani , Richard Joseph Niescier , Geoffrey Lawrence Smith , Walter G. Soto , Daniel K. Greenwood
IPC分类号： G06F12/00 , G06F12/06
CPC分类号： G06F12/0607
摘要： A multiple agent system providing each of a plurality of agents, e.g., processors, to access a shared synchronous or asynchronous memory. In the case of synchronous memory, the clock signal from a super agent selected from among the plurality of agents provides a memory access clock signal to the other agents accessing the same shared memory. The other agents synchronize their respective address, data and control busses to those of the super agent, and output a representation of the same clock signal to the shared memory. In another aspect of the present invention, the shared memory is partitioned for use from among a plurality of groups of agents, each agent group comprising one or more agents. Any one of the agents may update a configuration register to flexibly reconfigure the amount of shared memory available to the agents as necessary.
摘要翻译：提供多个代理（例如处理器）中的每一个以访问共享同步或异步存储器的多代理系统。在同步存储器的情况下，从多个代理中选择的来自超级代理的时钟信号向访问同一共享存储器的其他代理提供存储器访问时钟信号。其他代理将其各自的地址，数据和控制总线同步到超级代理的总线，并将相同时钟信号的表示输出到共享存储器。在本发明的另一方面，共享存储器被划分为在多组代理之间使用，每个代理组包括一个或多个代理。任何一个代理可以更新配置寄存器，以便根据需要灵活地重新配置代理可用的共享内存量。

4. 发明授权

US06230215B1 On-demand transfer engine 有权
标题翻译：按需传输引擎
公开(公告)号：US06230215B1
公开(公告)日：2001-05-08
申请号：US09188904
申请日：1998-11-10
申请人： Jalil Fadavi-Ardekani , Srinivasa Gutta , Walter G. Soto , Avinash Velingker , Daniel K. Greenwood
发明人： Jalil Fadavi-Ardekani , Srinivasa Gutta , Walter G. Soto , Avinash Velingker , Daniel K. Greenwood
IPC分类号： G06F300
CPC分类号： G06F1/3237 , G06F1/3203 , G06F11/349 , G06F12/0646 , H04L7/0004 , H04L7/0025 , H04L7/0029 , H04L7/0278 , Y02D10/128 , Y02D10/34
摘要： An on-demand transfer (ODT) engine is located in each peripheral in a host/peripheral system communicating using a burst mode bus, e.g., a PCI bus. Each peripheral transfers blocks by setting, e.g., a starting address and block size of a data block to be transferred. Importantly, the starting location of a data transfer stream is maintained in a common memory area, e.g., in the host, while the length of the data transfer block is maintained in the ODT engine. By maintaining the length of the data block in the ODT engine, the peripheral can change the length of a block in a continual data stream on the fly, without the need to communicate with the host computer or common data transfer device such as a DMA. In the disclosed embodiment, up to 128 data streams may be simultaneously transferred.
摘要翻译：按需传输（ODT）引擎位于使用突发模式总线（例如PCI总线）通信的主机/外围设备系统的每个外围设备中。每个外设通过设置例如要传送的数据块的起始地址和块大小来传送块。重要的是，数据传输流的起始位置保持在公共存储器区域中，例如在主机中，而数据传输块的长度保持在ODT引擎中。通过保持ODT引擎中数据块的长度，外设可以随时更改连续数据流中块的长度，而无需与主机或公共数据传输设备（如DMA）通信。在所公开的实施例中，多达128个数据流可以被同时传送。

5. 发明授权

US06519711B1 Method and apparatus for controlling a clocked circuit having a register for storing a bit received from an input terminal and an output terminal connected to clock terminal of the clocked circuit 有权
标题翻译：用于控制时钟电路的方法和装置具有用于存储从输入端接收的位的寄存器和连接到时钟电路的时钟端的输出端
公开(公告)号：US06519711B1
公开(公告)日：2003-02-11
申请号：US09409309
申请日：1999-09-29
申请人： Frederick H. Fischer , Srinivasa Gutta , Vladimir Sindalovsky
发明人： Frederick H. Fischer , Srinivasa Gutta , Vladimir Sindalovsky
IPC分类号： G06F104
CPC分类号： G06F1/08
摘要： A method and apparatus for controlling a clock of a component of an integrated circuit for testing purposes. The clock is controlled on a hardware level. Specifically, a stepped clocking technique is provided by which a processor can advance the clock signal of a component one bit at a time or in rapid bursts of successive bits. This provides for operation of the accelerator block in increments of half-clock cycles (bit by bit). The accelerator block can be stopped during processing of the dataset. Registers of the accelerator block can then be interrogated by the processor, which continues to operate at full clock speed, to determine how the accelerator block is processing the data.
摘要翻译：一种用于控制用于测试目的的集成电路的部件的时钟的方法和装置。时钟在硬件级别进行控制。具体地说，提供了一种阶梯式时钟技术，通过该阶梯式时钟技术，处理器可以一次一个位或者连续位的快速突发中提前一个分量的时钟信号。这提供了以半时钟周期（逐位）为增量的加速器块的操作。加速器块可以在处理数据集时停止。然后可以由继续以全时钟速度运行的处理器询问加速器块的寄存器，以确定加速器块如何处理数据。

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