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1. 发明申请

US20090265028A1 Organic Substrate with Asymmetric Thickness for Warp Mitigation 审中-公开
标题翻译：用于经纱缓解的不对称厚度的有机基材
公开(公告)号：US20090265028A1
公开(公告)日：2009-10-22
申请号：US12107064
申请日：2008-04-21
申请人： Sri M. Sri-Jayantha , Arun Sharma , Vijayeshwar D. Khanna , Hien P. Dang , David J. Russell , Douglas O. Powell
发明人： Sri M. Sri-Jayantha , Arun Sharma , Vijayeshwar D. Khanna , Hien P. Dang , David J. Russell , Douglas O. Powell
IPC分类号： G06F19/00
CPC分类号： H05K3/0005 , H05K1/0271 , H05K3/4602 , H05K3/4626 , H05K2201/0191 , H05K2201/09136
摘要： A process for large scale production of a laminated organic substrate having reduced thermal warp.
摘要翻译：用于大规模生产具有降低的热翘曲的层压有机基材的方法。

2. 发明授权

US07759787B2 Packaging substrate having pattern-matched metal layers 失效
标题翻译：具有图案匹配金属层的包装基板
公开(公告)号：US07759787B2
公开(公告)日：2010-07-20
申请号：US11935834
申请日：2007-11-06
申请人： Sri M. Sri-Jayantha , Hien P. Dang , Vijayeshwar D. Khanna , Arun Sharma
发明人： Sri M. Sri-Jayantha , Hien P. Dang , Vijayeshwar D. Khanna , Arun Sharma
IPC分类号： H01L23/053 , H01L23/12
CPC分类号： H05K1/0271 , H01L23/49833 , H01L23/49838 , H01L2924/0002 , H05K3/0005 , H05K3/4644 , H05K2201/09136 , H05K2201/09227 , H05K2203/1572 , Y10T29/49004 , Y10T29/49155 , H01L2924/00
摘要： A pattern matched pair of a front metal interconnect layer and a back metal interconnect layer having matched thermal expansion coefficients are provided for a reduced warp packaging substrate. Metal interconnect layers containing a high density of wiring and complex patterns are first developed so that interconnect structures for signal transmission are optimized for electrical performance. Metal interconnect layers containing a low density wiring and relatively simple patterns are then modified to match the pattern of a mirror image metal interconnect layer located on the opposite side of the core and the same number of metal interconnect layer away from the core. During this pattern-matching process, the contiguity of electrical connection in the metal layers with a low density wiring may become disrupted. The disruption is healed by an additional design step in which the contiguity of the electrical connection in the low density is reestablished.
摘要翻译：提供具有匹配的热膨胀系数的前金属互连层和背金属互连层的图案匹配对，用于经缩短的经向包装基板。首先开发了包含高密度布线和复杂图案的金属互连层，使得用于信号传输的互连结构被优化用于电性能。然后修改包含低密度布线和相对简单图案的金属互连层，以匹配位于芯的相对侧上的镜像金属互连层的图案和与芯相距相同数量的金属互连层。在这种模式匹配过程中，具有低密度布线的金属层中的电连接的连续性可能会被破坏。通过额外的设计步骤来治愈中断，其中重新建立低密度电连接的邻接性。

3. 发明申请

US20090114429A1 PACKAGING SUBSTRATE HAVING PATTERN-MATCHED METAL LAYERS 失效
标题翻译：包装与图案匹配的金属层的衬底
公开(公告)号：US20090114429A1
公开(公告)日：2009-05-07
申请号：US11935834
申请日：2007-11-06
申请人： Sri M. Sri-Jayantha , Hien P. Dang , Vijayeshwar D. Khanna , Arun Sharma
发明人： Sri M. Sri-Jayantha , Hien P. Dang , Vijayeshwar D. Khanna , Arun Sharma
IPC分类号： H05K1/03 , G06F17/50 , H05K3/00
CPC分类号： H05K1/0271 , H01L23/49833 , H01L23/49838 , H01L2924/0002 , H05K3/0005 , H05K3/4644 , H05K2201/09136 , H05K2201/09227 , H05K2203/1572 , Y10T29/49004 , Y10T29/49155 , H01L2924/00
摘要： A pattern matched pair of a front metal interconnect layer and a back metal interconnect layer having matched thermal expansion coefficients are provided for a reduced warp packaging substrate. Metal interconnect layers containing a high density of wiring and complex patterns are first developed so that interconnect structures for signal transmission are optimized for electrical performance. Metal interconnect layers containing a low density wiring and relatively simple patterns are then modified to match the pattern of a mirror image metal interconnect layer located on the opposite side of the core and the same number of metal interconnect layer away from the core. During this pattern-matching process, the contiguity of electrical connection in the metal layers with a low density wiring may become disrupted. The disruption is healed by an additional design step in which the contiguity of the electrical connection in the low density is reestablished.
摘要翻译：提供具有匹配的热膨胀系数的前金属互连层和背金属互连层的图案匹配对，用于经缩短的经向包装基板。首先开发了包含高密度布线和复杂图案的金属互连层，使得用于信号传输的互连结构被优化用于电性能。然后修改包含低密度布线和相对简单图案的金属互连层，以匹配位于芯的相对侧上的镜像金属互连层的图案和与芯相距相同数量的金属互连层。在这种模式匹配过程中，具有低密度布线的金属层中的电连接的连续性可能会被破坏。通过额外的设计步骤来治愈中断，其中重新建立低密度电连接的邻接性。

4. 发明授权

US07901998B2 Packaging substrate having pattern-matched metal layers 有权
标题翻译：具有图案匹配金属层的包装基板
公开(公告)号：US07901998B2
公开(公告)日：2011-03-08
申请号：US12775970
申请日：2010-05-07
申请人： Sri M. Sri-Jayantha , Hien P. Dang , Vijayeshwar D. Khanna , Arun Sharma
发明人： Sri M. Sri-Jayantha , Hien P. Dang , Vijayeshwar D. Khanna , Arun Sharma
IPC分类号： H01L21/44 , H01L21/48
CPC分类号： H05K1/0271 , H01L23/49833 , H01L23/49838 , H01L2924/0002 , H05K3/0005 , H05K3/4644 , H05K2201/09136 , H05K2201/09227 , H05K2203/1572 , Y10T29/49004 , Y10T29/49155 , H01L2924/00
摘要： A pattern matched pair of a front metal interconnect layer and a back metal interconnect layer having matched thermal expansion coefficients are provided for a reduced warp packaging substrate. Metal interconnect layers containing a high density of wiring and complex patterns are first developed so that interconnect structures for signal transmission are optimized for electrical performance. Metal interconnect layers containing a low density wiring and relatively simple patterns are then modified to match the pattern of a mirror image metal interconnect layer located on the opposite side of the core and the same number of metal interconnect layer away from the core. During this pattern-matching process, the contiguity of electrical connection in the metal layers with a low density wiring may become disrupted. The disruption is healed by an additional design step in which the contiguity of the electrical connection in the low density is reestablished.
摘要翻译：提供具有匹配的热膨胀系数的前金属互连层和背金属互连层的图案匹配对，用于经缩短的经向包装基板。首先开发了包含高密度布线和复杂图案的金属互连层，使得用于信号传输的互连结构被优化用于电性能。然后修改包含低密度布线和相对简单图案的金属互连层，以匹配位于芯的相对侧上的镜像金属互连层的图案和与芯相距相同数量的金属互连层。在这种模式匹配过程中，具有低密度布线的金属层中的电连接的连续性可能会被破坏。通过额外的设计步骤来治愈中断，其中重新建立低密度电连接的邻接性。

5. 发明申请

US20100218364A1 PACKAGING SUBSTRATE HAVING PATTERN-MATCHED METAL LAYERS 有权
标题翻译：包装与图案匹配的金属层的衬底
公开(公告)号：US20100218364A1
公开(公告)日：2010-09-02
申请号：US12775970
申请日：2010-05-07
申请人： Sri M. Sri-Jayantha , Hien P. Dang , Vijayeshwar D. Khanna , Arun Sharma
发明人： Sri M. Sri-Jayantha , Hien P. Dang , Vijayeshwar D. Khanna , Arun Sharma
IPC分类号： H05K3/22
CPC分类号： H05K1/0271 , H01L23/49833 , H01L23/49838 , H01L2924/0002 , H05K3/0005 , H05K3/4644 , H05K2201/09136 , H05K2201/09227 , H05K2203/1572 , Y10T29/49004 , Y10T29/49155 , H01L2924/00
摘要： A pattern matched pair of a front metal interconnect layer and a back metal interconnect layer having matched thermal expansion coefficients are provided for a reduced warp packaging substrate. Metal interconnect layers containing a high density of wiring and complex patterns are first developed so that interconnect structures for signal transmission are optimized for electrical performance. Metal interconnect layers containing a low density wiring and relatively simple patterns are then modified to match the pattern of a mirror image metal interconnect layer located on the opposite side of the core and the same number of metal interconnect layer away from the core. During this pattern-matching process, the contiguity of electrical connection in the metal layers with a low density wiring may become disrupted. The disruption is healed by an additional design step in which the contiguity of the electrical connection in the low density is reestablished.
摘要翻译：提供具有匹配的热膨胀系数的前金属互连层和背金属互连层的图案匹配对，用于经缩短的经向包装基板。首先开发了包含高密度布线和复杂图案的金属互连层，使得用于信号传输的互连结构被优化用于电性能。然后修改包含低密度布线和相对简单图案的金属互连层，以匹配位于芯的相对侧上的镜像金属互连层的图案和与芯相距相同数量的金属互连层。在这种模式匹配过程中，具有低密度布线的金属层中的电连接的连续性可能会被破坏。通过额外的设计步骤来治愈中断，其中重新建立低密度电连接的邻接性。

6. 发明申请

US20080116571A1 Structures to enhance cooling of computer memory modules 失效
标题翻译：用于增强计算机内存模块冷却的结构
公开(公告)号：US20080116571A1
公开(公告)日：2008-05-22
申请号：US11604152
申请日：2006-11-22
申请人： Hien P. Dang , Vinod Kamath , Vijayeshwar D. Khanna , Gerard McVicker , Sri M. Sri-Jayantha , Jung H. Yoon
发明人： Hien P. Dang , Vinod Kamath , Vijayeshwar D. Khanna , Gerard McVicker , Sri M. Sri-Jayantha , Jung H. Yoon
IPC分类号： H01L23/467
CPC分类号： H01L23/4093 , H01L23/3672 , H01L23/467 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A spring-like cooling structure for an in-line chip module is formed from a continuous sheet of a thermally conducting material having a front side and a back side, the sheet folded at substantially a one-hundred and eighty degree angle, wherein a length of the structure substantially correlates to a length of the in-line chip module, and a width of the structure is wider than a width of the in-line chip module such that the structure fits over and substantially around the in-line chip module; openings at a left-side, right-side and a bottom of the structure for easily affixing and removing the structure from the in-line chip module; a top part comprising a top surface disposed over a top of the in-line chip module when affixed to the in-line chip module, and comprising an angled surface flaring outward from the in-line chip module, the angled surface positioned directly beneath the top surface; a center horizontal part; a gap between the center horizontal part and the plurality of chips; and a flared bottom area of the structure.
摘要翻译：用于直列芯片模块的弹簧状冷却结构由具有前侧和后侧的导热材料的连续片材形成，所述片材以基本上以一百八十度的角度折叠，其中长度的结构基本上与直列芯片模块的长度相关，并且该结构的宽度比直列芯片模块的宽度宽，使得该结构适合于并且基本上围绕在线芯片模块; 在结构的左侧，右侧和底部的开口，用于容易地从线内芯片模块固定和移除结构; 顶部，其包括顶部表面，所述顶部表面设置在所述直列芯片模块的顶部上，当固定到所述在线芯片模块时，并且包括从所述直列芯片模块向外扩张的成角度的表面，顶面中心水平部分; 中心水平部分和多个芯片之间的间隙; 和结构的扩口底部区域。

7. 发明授权

US07612446B2 Structures to enhance cooling of computer memory modules 失效
标题翻译：用于增强计算机内存模块冷却的结构
公开(公告)号：US07612446B2
公开(公告)日：2009-11-03
申请号：US11604152
申请日：2006-11-22
申请人： Hien P. Dang , Vinod Kamath , Vijayeshwar D. Khanna , Gerard McVicker , Sri M. Sri-Jayantha , Jung H. Yoon
发明人： Hien P. Dang , Vinod Kamath , Vijayeshwar D. Khanna , Gerard McVicker , Sri M. Sri-Jayantha , Jung H. Yoon
IPC分类号： H01L23/34 , H05K7/20 , H01L21/00 , F28F7/00
CPC分类号： H01L23/4093 , H01L23/3672 , H01L23/467 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A spring-like cooling structure for an in-line chip module is formed from a continuous sheet of a thermally conducting material having a front side and a back side, the sheet folded at substantially a one-hundred and eighty degree angle, wherein a length of the structure substantially correlates to a length of the in-line chip module, and a width of the structure is wider than a width of the in-line chip module such that the structure fits over and substantially around the in-line chip module; openings at a left-side, right-side and a bottom of the structure for easily affixing and removing the structure from the in-line chip module; a top part comprising a top surface disposed over a top of the in-line chip module when affixed to the in-line chip module, and comprising an angled surface flaring outward from the in-line chip module, the angled surface positioned directly beneath the top surface; a center horizontal part; a gap between the center horizontal part and the plurality of chips; and a flared bottom area of the structure.
摘要翻译：用于直列芯片模块的弹簧状冷却结构由具有前侧和后侧的导热材料的连续片材形成，所述片材以基本上以一百八十度的角度折叠，其中长度的结构基本上与直列芯片模块的长度相关，并且该结构的宽度比直列芯片模块的宽度宽，使得该结构适合于并且基本上围绕在线芯片模块; 在结构的左侧，右侧和底部的开口，用于容易地从线内芯片模块固定和移除结构; 顶部，其包括顶部表面，所述顶部表面设置在所述直列芯片模块的顶部上，当固定到所述在线芯片模块时，并且包括从所述直列芯片模块向外扩张的成角度的表面，顶面中心水平部分; 中心水平部分和多个芯片之间的间隙; 和结构的扩口底部区域。

8. 发明授权

US07777301B2 Electronic components on trenched substrates and method of forming same 有权
公开(公告)号：US07777301B2
公开(公告)日：2010-08-17
申请号：US12099412
申请日：2008-04-08
申请人： David Questad , Vijayeshwar D. Khanna , Jennifer V. Muncy , Arun Sharma , Sri M. Sri-Jayantha , Lorenzo Valdevit
发明人： David Questad , Vijayeshwar D. Khanna , Jennifer V. Muncy , Arun Sharma , Sri M. Sri-Jayantha , Lorenzo Valdevit
IPC分类号： H01L23/48
CPC分类号： H01L28/40 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00011 , H01L2924/00014 , H01L2924/15174 , H01L2924/15311 , H05K1/0231 , H05K1/0271 , H05K1/111 , H05K3/3436 , H05K3/3442 , H05K2201/09036 , H05K2201/10015 , H05K2201/10727 , Y02P70/613 , Y10T29/4913 , Y10T428/24479 , H01L2224/0401 , H01L2924/00
摘要： A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.

9. 发明授权

US07732894B2 Electronic components on trenched substrates and method of forming same 失效
公开(公告)号：US07732894B2
公开(公告)日：2010-06-08
申请号：US12030274
申请日：2008-02-13
申请人： David Questad , Vijayeshwar D. Khanna , Jennifer V. Muney , Arun Sharma , Sri M. Sri-Jayantha , Lorenzo Valdevit
发明人： David Questad , Vijayeshwar D. Khanna , Jennifer V. Muney , Arun Sharma , Sri M. Sri-Jayantha , Lorenzo Valdevit
IPC分类号： H01L23/48
CPC分类号： H01L28/40 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00011 , H01L2924/00014 , H01L2924/15174 , H01L2924/15311 , H05K1/0231 , H05K1/0271 , H05K1/111 , H05K3/3436 , H05K3/3442 , H05K2201/09036 , H05K2201/10015 , H05K2201/10727 , Y02P70/613 , Y10T29/4913 , Y10T428/24479 , H01L2224/0401 , H01L2924/00
摘要： A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.

10. 发明申请

US20080218990A1 ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME 有权
公开(公告)号：US20080218990A1
公开(公告)日：2008-09-11
申请号：US12099381
申请日：2008-04-08
申请人： David Questad , Vijayeshwar D. Khanna , Jennifer V. Muncy , Arun Sharma , Sri M. Sri-Jayantha , Lorenzo Valdevit
发明人： David Questad , Vijayeshwar D. Khanna , Jennifer V. Muncy , Arun Sharma , Sri M. Sri-Jayantha , Lorenzo Valdevit
IPC分类号： H05K7/00
CPC分类号： H01L28/40 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00011 , H01L2924/00014 , H01L2924/15174 , H01L2924/15311 , H05K1/0231 , H05K1/0271 , H05K1/111 , H05K3/3436 , H05K3/3442 , H05K2201/09036 , H05K2201/10015 , H05K2201/10727 , Y02P70/613 , Y10T29/4913 , Y10T428/24479 , H01L2224/0401 , H01L2924/00
摘要： A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.

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