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1. 发明授权

US09336890B1 Simultaneous programming of many bits in flash memory 有权
标题翻译：闪存中许多位的同时编程
公开(公告)号：US09336890B1
公开(公告)日：2016-05-10
申请号：US14517201
申请日：2014-10-17
申请人： Spansion LLC
发明人： Kaoru Mori
IPC分类号： G11C16/26 , G11C16/24 , G11C7/10 , G11C7/06
CPC分类号： G11C16/26 , G11C5/025 , G11C7/06 , G11C7/1069 , G11C7/18 , G11C16/10 , G11C16/24
摘要： A semiconductor device includes: a plurality of memory cells; a plurality of local bit lines connected to respective memory cells of the plurality of memory cells; and a first amplifier. The first amplifier receives read data from each local bit line of the plurality of local bit lines and determines a transition speed of an output level of the first amplifier in response to receiving a combination of at least two pieces of read data. The first amplifier transfers, based on the determined transition speed, multivalued data of the read data to a read global bit line.
摘要翻译：半导体器件包括：多个存储单元; 连接到所述多个存储器单元中的相应存储单元的多个局部位线; 和第一放大器。第一放大器从多个本地位线的每个本地位线接收读取数据，并响应于接收到至少两条读取数据的组合来确定第一放大器的输出电平的转变速度。第一放大器基于所确定的转换速度将读取的数据的多值数据传送到读出的全局位线。

2. 发明申请

US20160111166A1 Simultaneous Programming of Many Bits in Flash Memory 有权
标题翻译：闪存中许多位的同步编程
公开(公告)号：US20160111166A1
公开(公告)日：2016-04-21
申请号：US14517201
申请日：2014-10-17
申请人： Spansion LLC
发明人： Kaoru Mori
IPC分类号： G11C16/26 , G11C16/24
CPC分类号： G11C16/26 , G11C5/025 , G11C7/06 , G11C7/1069 , G11C7/18 , G11C16/10 , G11C16/24
摘要： A semiconductor device includes: a plurality of memory cells; a plurality of local bit lines connected to respective memory cells of the plurality of memory cells; and a first amplifier. The first amplifier receives read data from each local bit line of the plurality of local bit lines and determines a transition speed of an output level of the first amplifier in response to receiving a combination of at least two pieces of read data. The first amplifier transfers, based on the determined transition speed, multivalued data of the read data to a read global bit line.
摘要翻译：半导体器件包括：多个存储单元; 连接到所述多个存储器单元中的相应存储单元的多个局部位线; 和第一放大器。第一放大器从多个本地位线的每个本地位线接收读取数据，并响应于接收到至少两条读取数据的组合来确定第一放大器的输出电平的转变速度。第一放大器基于所确定的转换速度将读取的数据的多值数据传送到读出的全局位线。

3. 发明授权

US09224487B2 Semiconductor memory read and write access 有权
标题翻译：半导体存储器读写访问
公开(公告)号：US09224487B2
公开(公告)日：2015-12-29
申请号：US13749246
申请日：2013-01-24
申请人： Spansion LLC
发明人： Kaoru Mori , Toshiya Uchida
IPC分类号： G11C11/06 , G11C16/26 , G11C7/18 , G11C7/22 , G11C16/24 , G11C16/32
CPC分类号： G11C16/26 , G11C7/18 , G11C7/227 , G11C16/24 , G11C16/32
摘要： A semiconductor memory includes a sense amplifier which operates in response to activation of a sense amplifier enable signal and determines logic held in a nonvolatile memory cell according to a voltage of a bit line, the voltage varying with a cell current flowing through a real cell transistor, a replica cell transistor coupled in series between a first node and a ground line, and a timing generation unit. The timing generation unit activates the sense amplifier enable signal when the first node coupled to the ground line via the replica cell transistor changes from a high level to a low level. The replica cell transistor includes a control gate receiving a constant voltage and a floating gate coupled to the control gate. Thus, the activation timing of the sense amplifier can be optimally set in accordance with the electric characteristic of the memory cell.
摘要翻译：半导体存储器包括读出放大器，其响应于读出放大器使能信号的激活而操作，并且根据位线的电压确定保持在非易失性存储器单元中的逻辑，该电压随着流过真实单元晶体管的单元电流而变化耦合在第一节点和地线之间的复制单元晶体管，以及定时产生单元。当通过复制单元晶体管耦合到接地线的第一节点从高电平变为低电平时，定时生成单元激活读出放大器使能信号。复制单元晶体管包括接收恒定电压的控制栅极和耦合到控制栅极的浮置栅极。因此，可以根据存储单元的电特性来最佳地设置读出放大器的激活定时。

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