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1. 发明授权

US11190140B2 Wide voltage trans-impedance amplifier 有权
公开(公告)号：US11190140B2
公开(公告)日：2021-11-30
申请号：US16967745
申请日：2020-04-30
申请人： SOUTHEAST UNIVERSITY
发明人： Chao Chen , Jun Yang , Xinning Liu
IPC分类号： H03F1/02 , H03F1/56
摘要： A wide voltage trans-impedance amplifier includes a first P-channel metal oxide semiconductor (PMOS) transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a first bias voltage VB1, a second bias voltage VB2, a third bias voltage VB3, a first N-channel metal oxide semiconductor (NMOS) transistor NM1, and a second NMOS transistor NM2. A common-gate amplifier detects a change of an input voltage, and a negative feedback is constructed by injecting a current into a current mirror to achieve a low input impedance. The trans-impedance amplifier uses a common-gate amplifier to monitor an input voltage and uses a current mirror to perform the transconductance enhancement on an input transistor, while ensuring a relatively high loop gain.

2. 发明授权

US11168623B2 Nonlinear disturbance rejection control apparatus and method for electronic throttle control systems 有权
公开(公告)号：US11168623B2
公开(公告)日：2021-11-09
申请号：US16618380
申请日：2018-11-20
申请人： SOUTHEAST UNIVERSITY
发明人： Shihua Li , Chen Dai , Jun Yang , Hao Sun , Xiangyu Wang , Qi Li
IPC分类号： F02D41/00 , F02D9/10 , G05B13/04
摘要： A nonlinear disturbance rejection control apparatus and method for electronic throttle control systems are invented to control the electronic throttle system and to achieve a continuous finite-time disturbance rejection control goal. A control sub-apparatus and method are proposed with an observing sub-apparatus and method for controlling the opening angle of an electronic throttle valve. A mathematical model of the electronic throttle system is analyzed and a control-oriented model is presented with the formation of a lumped disturbance. With combination of the continuous terminal sliding mode control method and the output feedback control method, based on the finite-time high-order sliding mode observer, the preferred control performance is guaranteed, where both the dynamic and static performance of the system is effectively improved.

3. 发明授权

US11139805B1 Bi-directional adaptive clocking circuit supporting a wide frequency range 有权
公开(公告)号：US11139805B1
公开(公告)日：2021-10-05
申请号：US16957724
申请日：2019-07-09
申请人： SOUTHEAST UNIVERSITY
发明人： Weiwei Shan , Jun Yang , Longxing Shi
IPC分类号： H03K5/14 , H03K5/131 , G04F10/00 , H03K5/00 , G06F1/08
摘要： A two-way adaptive clock circuit supporting a wide frequency range is composed of a phase clock generating module, a phase clock selecting module, an adaptive clock stretching or compressing amount regulating circuit module and a control module. The adaptive clock stretching or compressing amount regulating circuit module can monitor delay information of a critical path in a chip in real time and feed the information back into the control module. After receiving a clock stretching or compressing enable signal and a stretching or compressing scale signal, the control module selects a target phase clock from clocks generated by the phase clock generating module to rapidly regulate an adaptive clock in a current cycle. The present invention is applied to an adaptive voltage frequency regulating circuit based on on-line time sequence monitoring.

4. 发明授权

US10648816B2 Device and method for integrated navigation based on wireless fingerprints and MEMS sensors 有权
公开(公告)号：US10648816B2
公开(公告)日：2020-05-12
申请号：US15536615
申请日：2015-11-30
申请人： SOUTHEAST UNIVERSITY
发明人： Yuan Zhuang , Jun Yang , Longning Qi
IPC分类号： G01C21/16 , G01S5/02 , G01C21/20 , H04W4/021 , H04W84/06 , G01C21/00 , G01S5/00
摘要： An integration navigation device and method in which wireless signal strength data collecting and processing module obtains first position information of a target to be detected; a MEMS sensor data collecting and processing module obtains, according to state change information of the target to be detected, second position information of the target to be detected; a data integration module integrates the first position information and the second position information and feeds back the integrated result to the wireless signal strength data collecting and processing module and the MEMS sensor data collecting and processing module to perform data processing of the next moment.

5. 发明授权

US09734056B2 Cache structure and management method for use in implementing reconfigurable system configuration information storage 有权
公开(公告)号：US09734056B2
公开(公告)日：2017-08-15
申请号：US14425456
申请日：2013-11-13
申请人： Southeast University
发明人： Longxing Shi , Jun Yang , Peng Cao , Bo Liu , Jinjiang Yang , Leibo Liu , Shouyi Yin , Shaojun Wei
IPC分类号： G06F12/06 , G06F12/08 , G06F17/50 , G06F12/0811 , G06F12/0895
CPC分类号： G06F12/0646 , G06F12/0811 , G06F12/0895 , G06F17/5054 , G06F2212/283 , G06F2212/601
摘要： A cache structure for use in implementing reconfigurable system configuration information storage, comprises: layered configuration information cache units: for use in caching configuration information that may be used by a certain or several reconfigurable arrays within a period of time; an off-chip memory interface module: for use in establishing communication; a configuration management unit: for use in managing a reconfiguration process of the reconfigurable arrays, in mapping each subtask in an algorithm application to a certain reconfigurable array, thus the reconfigurable array will, on the basis of the mapped subtask, load the corresponding configuration information to complete a function reconfiguration for the reconfigurable array. This increases the utilization efficiency of configuration information caches. Also provided is a method for managing the reconfigurable system configuration information caches, employing a mixed priority cache update method, and changing a mode for managing the configuration information caches in a conventional reconfigurable system, thus increasing the dynamic reconfiguration efficiency in a complex reconfigurable system.

6. 发明申请

US20170219649A1 Process Corner Detection Circuit Based on Self-Timing Oscillation Ring 审中-公开
公开(公告)号：US20170219649A1
公开(公告)日：2017-08-03
申请号：US15321111
申请日：2014-12-26
申请人： Southeast University
发明人： Weiwei Shan , Longxing Shi , Jun Yang
IPC分类号： G01R31/28 , H03K3/03
摘要： A process corner detection circuit based on a self-timing oscillation ring comprises a reset circuit (1), the self-timing oscillation ring (2), and a counting module (3). The self-timing oscillation ring (2) consists of m two-input Miller units and inverters, and a two-input AND gate, m being a positive integer greater than or equal to 3. The circuit can be used for detecting a process corner of a fabricated integrated circuit chip, and reflecting the process corner of the chip according to the number of oscillations of the self-timing oscillation ring (2). The number of oscillations of the self-timing oscillation ring (2) in different process corners is acquired by Hspice simulation before the chip tape-out, and the process corner of the chip after the chip tape-out can be determined according to the actually measured number of oscillations.

7. 发明授权

US09632937B2 Pre-decoding analysis based configuration information cache management method and system 有权
公开(公告)号：US09632937B2
公开(公告)日：2017-04-25
申请号：US14430411
申请日：2013-11-13
申请人： Southeast University
发明人： Peng Cao , Jun Yang , Longxing Shi , Bo Liu , Jinjiang Yang , Leibo Liu , Shouyi Yin , Shaojun Wei
IPC分类号： G06F12/08 , G06F12/0862 , G06F3/06 , G06F17/50 , H04L29/08
CPC分类号： G06F12/0862 , G06F3/0604 , G06F3/0631 , G06F3/0673 , G06F17/5054 , G06F2212/1041 , G06F2212/601 , G06F2212/602 , G06F2212/6028 , H04L67/2842
摘要： Disclosed are a pre-decoding analysis-based configuration information cache management system, comprising a streaming media processing module, a configuration information prefetch FIFO module, a configuration information storage unit, and a cache controller module. Also disclosed is a management method for the pre-decoding analysis-based configuration information cache management system. The present invention allows for increased dynamic reconfiguration efficiency of a large-scale coarse-grained reconfigurable system.

8. 发明授权

US11651766B2 Ultra-low-power speech feature extraction circuit based on non-overlapping framing and serial FFT 有权
公开(公告)号：US11651766B2
公开(公告)日：2023-05-16
申请号：US17181908
申请日：2021-02-22
申请人： SOUTHEAST UNIVERSITY
发明人： Weiwei Shan , Lixuan Zhu , Jun Yang , Longxing Shi
IPC分类号： G10L15/02 , G06F17/14 , G10L25/24
CPC分类号： G10L15/02 , G06F17/142 , G10L25/24
摘要： The present invention discloses an ultra-low-power speech feature extraction circuit based on non-overlapping framing and serial fast Fourier transform (FFT), and belongs to the technical field of computation, calculation or counting. The circuit is oriented to the field of intelligence, and is integrally composed of a pre-process module, a windowing module, a Fourier transform module, a Mel filtering module, an adjacent frame merging module, a discrete cosine transform (DCT) module and other modules by optimizing the architecture of a Mel-frequency Cepstral Coefficients (MFCC) algorithm. Large-scale storage caused by framing is avoided in a non-overlapping framing mode, storage contained in the MFCC algorithm is further reduced, and the circuit area and the power consumption are greatly reduced. An FFT algorithm in the feature extraction circuit adopts a serial pipeline mode to process data, makes full use of the characteristics of serial inflow of audio data, and further reduces the storage area and operations of the circuit.

9. 发明授权

US11290009B2 High energy efficiency switched-capacitor power converter 有权
公开(公告)号：US11290009B2
公开(公告)日：2022-03-29
申请号：US16966474
申请日：2020-04-30
申请人： SOUTHEAST UNIVERSITY
发明人： Chao Chen , Jun Yang , Xinning Liu
IPC分类号： H02M3/07 , H02M1/00
摘要： A high energy efficiency switched-capacitor power converter includes the transmission gates T1-T7, the capacitors C1-C4, the load capacitor CL, and resistors, PMOS tubes and NMOS tubes. The power converter converts a stable input voltage of 3V into an output voltage of 1V by means of charge transfer. In the state of timing sequence 1, the on-chip capacitor C1, the capacitor C2 and the load capacitor CL are charged in series. In the state of timing sequence 2, the capacitor C1 and the capacitor C2 are connected in parallel to the capacitor CL to supplement the charge loss due to load for the capacitor CL. When the establishment is completed, the voltages across the capacitor C1, the capacitor C2, and the capacitor CL are basically the same. At this time, the voltage drop across the switch tube approximates 0 V during the charge transfer process.

10. 发明授权

US09236115B2 Circuit for enhancing robustness of sub-threshold SRAM memory cell 有权
标题翻译：用于增强子阈值SRAM存储单元鲁棒性的电路
公开(公告)号：US09236115B2
公开(公告)日：2016-01-12
申请号：US14369651
申请日：2012-12-27
申请人： SOUTHEAST UNIVERSITY
发明人： Na Bai , Longxing Shi , Jun Yang , Xinning Liu , Jiafeng Zhu , Yue Feng , Cai Gong , Fei Pan , Hong Chang , Yifeng Deng , Yuan Chen , Yingcheng Xia
IPC分类号： G11C11/419 , G11C11/417 , H01L27/11 , G11C11/412
CPC分类号： G11C11/419 , G11C11/412 , G11C11/417 , H01L27/1104
摘要： A circuit for improving process robustness of sub-threshold SRAM memory cells serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to PMOS transistors of the sub-threshold SRAM memory cell and substrate of PMOS transistors in the circuit. The circuit includes a detection circuit for threshold voltages of the PMOS transistors and a differential input and single-ended output amplifier. The circuit changes the substrate voltage of the PMOS transistors in the sub-threshold SRAM memory cell and the PMOS transistors in the circuit in a self-adapting manner by detecting threshold voltage fluctuations of PMOS and NMOS transistor resulted from process fluctuations and thereby regulates the threshold voltages of the PMOS transistors, so that the threshold voltages of the PMOS and NMOS transistors match. The circuit improves the noise margin of sub-threshold SRAM memory cells and the process robustness of sub-threshold SRAM memory cells.
摘要翻译：用于提高子阈值SRAM存储单元的工艺稳健性的电路用作子阈值SRAM存储单元的辅助电路。电路的输出端连接到子阈值SRAM存储单元的PMOS晶体管和电路中PMOS晶体管的衬底。该电路包括用于PMOS晶体管的阈值电压的检测电路和差分输入和单端输出放大器。该电路通过检测来自过程波动的PMOS和NMOS晶体管的阈值电压波动，以自适应的方式改变子阈值SRAM存储单元中的PMOS晶体管的衬底电压和电路中的PMOS晶体管，从而调节阈值 PMOS晶体管的电压，使得PMOS和NMOS晶体管的阈值电压匹配。该电路提高了亚阈值SRAM存储单元的噪声容限和子阈值SRAM存储单元的工艺稳健性。

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