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1. 发明申请

US20100039095A1 Method of measuring flash memory cell current 有权
标题翻译：测量闪存单元电流的方法
公开(公告)号：US20100039095A1
公开(公告)日：2010-02-18
申请号：US12228691
申请日：2008-08-15
申请人： Boon-Aik Ang , Soo-yong Park , Steve Choi
发明人： Boon-Aik Ang , Soo-yong Park , Steve Choi
IPC分类号： G01R19/00
CPC分类号： G11C29/50 , G11C16/04 , G11C29/028 , G11C2029/5006
摘要： In the present method of measuring the current of a first current source, the current thereof may be combined with either the current of a second current source, or the current of a third current source. Based on a combination of the current of the first current source and either (a) the current of the second current source or (b) the current of the third current source, a digital output is provided. If this digital output is of a first value, the state of combining the current of the first current source with the current of the second current source becomes in effect. If this digital output is of a second value, the state of combining the current of the first current source with the current of the second current source becomes in effect.
摘要翻译：在本测量第一电流源的电流的方法中，其电流可以与第二电流源的电流或第三电流源的电流组合。基于第一电流源的电流和（a）第二电流源的电流或（b）第三电流源的电流的组合，提供数字输出。如果该数字输出是第一值，则将第一电流源的电流与第二电流源的电流组合的状态变为有效。如果该数字输出是第二值，则将第一电流源的电流与第二电流源的电流组合的状态变为有效。

2. 发明授权

US08581595B2 Method of measuring flash memory cell current 有权
标题翻译：测量闪存单元电流的方法
公开(公告)号：US08581595B2
公开(公告)日：2013-11-12
申请号：US12228691
申请日：2008-08-15
申请人： Boon-Aik Ang , Soo-yong Park , Steve Choi
发明人： Boon-Aik Ang , Soo-yong Park , Steve Choi
IPC分类号： G01R31/08
CPC分类号： G11C29/50 , G11C16/04 , G11C29/028 , G11C2029/5006
摘要： In the present method of measuring the current of a first current source, the current thereof may be combined with either the current of a second current source, or the current of a third current source. Based on a combination of the current of the first current source and either (a) the current of the second current source or (b) the current of the third current source, a digital output is provided. If this digital output is of a first value, the state of combining the current of the first current source with the current of the second current source becomes in effect. If this digital output is of a second value, the state of combining the current of the first current source with the current of the second current source becomes in effect.
摘要翻译：在本测量第一电流源的电流的方法中，其电流可以与第二电流源的电流或第三电流源的电流组合。基于第一电流源的电流和（a）第二电流源的电流或（b）第三电流源的电流的组合，提供数字输出。如果该数字输出是第一值，则将第一电流源的电流与第二电流源的电流组合的状态变为有效。如果该数字输出是第二值，则将第一电流源的电流与第二电流源的电流组合的状态变为有效。

3. 发明申请

US20100097876A1 APPARATUS AND METHOD FOR GENERATING WIDE-RANGE REGULATED SUPPLY VOLTAGES FOR A FLASH MEMORY 有权
标题翻译：用于产生FLASH存储器的宽范围调节电源电压的装置和方法
公开(公告)号：US20100097876A1
公开(公告)日：2010-04-22
申请号：US12255622
申请日：2008-10-21
申请人： Soo-Yong Park , Boon-Aik Ang , Steve Choi
发明人： Soo-Yong Park , Boon-Aik Ang , Steve Choi
IPC分类号： G11C5/14 , G05F1/10
CPC分类号： G11C5/147 , G05F1/56 , G11C8/10 , G11C16/30
摘要： A voltage regulator is provided. The voltage regulator provides an output voltage that is proportional to a digital multi-bit select signal. The voltage regulator includes a coarse voltage regulator and a fine voltage regulator. The coarse voltage regulator provides a coarse output voltage based on an output of a voltage divider selected based on the most significant bits of the select signal. The fine voltage regulator provides the output voltage from the coarse output voltage. The output of the fine voltage regulator is adjusted by adjusting the output of an adjustable current source that is provided to a resistor that is coupled between the output and one of the inputs of the fine voltage regulator.
摘要翻译：提供电压调节器。电压调节器提供与数字多位选择信号成比例的输出电压。电压调节器包括粗调电压调节器和精密电压调节器。粗电压调节器基于基于选择信号的最高有效位选择的分压器的输出提供粗略的输出电压。精细电压调节器提供粗输出电压的输出电压。微调电压调节器的输出通过调节可调电流源的输出来调节，该可调电流源提供给耦合在输出端和精密电压调节器的一个输入端之间的电阻器。

4. 发明授权

US07848167B2 Apparatus and method for generating wide-range regulated supply voltages for a flash memory 有权
标题翻译：用于产生用于闪速存储器的宽范围稳压电源电压的装置和方法
公开(公告)号：US07848167B2
公开(公告)日：2010-12-07
申请号：US12255622
申请日：2008-10-21
申请人： Soo-yong Park , Boon-Aik Ang , Steve Choi
发明人： Soo-yong Park , Boon-Aik Ang , Steve Choi
IPC分类号： G11C7/02 , G11C7/10 , G11C7/06
CPC分类号： G11C5/147 , G05F1/56 , G11C8/10 , G11C16/30
摘要： A voltage regulator is provided. The voltage regulator provides an output voltage that is proportional to a digital multi-bit select signal. The voltage regulator includes a coarse voltage regulator and a fine voltage regulator. The coarse voltage regulator provides a coarse output voltage based on an output of a voltage divider selected based on the most significant bits of the select signal. The fine voltage regulator provides the output voltage from the coarse output voltage. The output of the fine voltage regulator is adjusted by adjusting the output of an adjustable current source that is provided to a resistor that is coupled between the output and one of the inputs of the fine voltage regulator.
摘要翻译：提供电压调节器。电压调节器提供与数字多位选择信号成比例的输出电压。电压调节器包括粗调电压调节器和精密电压调节器。粗电压调节器基于基于选择信号的最高有效位选择的分压器的输出提供粗略的输出电压。精细电压调节器提供粗输出电压的输出电压。微调电压调节器的输出通过调节可调电流源的输出来调节，该可调电流源提供给耦合在输出端和精密电压调节器的一个输入端之间的电阻器。

5. 发明申请

US20070070703A1 Flash memory array system including a top gate memory cell 有权
公开(公告)号：US20070070703A1
公开(公告)日：2007-03-29
申请号：US11235901
申请日：2005-09-26
申请人： Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
发明人： Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

6. 发明授权

US08270213B2 Flash memory array system including a top gate memory cell 有权
标题翻译：包括顶栅存储单元的闪存阵列系统
公开(公告)号：US08270213B2
公开(公告)日：2012-09-18
申请号：US12962343
申请日：2010-12-07
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
IPC分类号： G11C16/12
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要翻译：存储器系统包括布置在扇区中的存储器单元。对应于扇区的解码器禁止具有缺陷顶门的存储单元。解码器可以包括用于禁用的低电压或高电压锁存器。包括顶栅处理算法。存储器系统可以包括动态顶栅耦合。包括具有顶栅处理的编程算法和波形。

7. 发明授权

US07778080B2 Flash memory array system including a top gate memory cell 有权
公开(公告)号：US07778080B2
公开(公告)日：2010-08-17
申请号：US12200930
申请日：2008-08-28
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
IPC分类号： G11C16/34
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

8. 发明授权

US06300400B1 Wallboard adhesive 失效
标题翻译：墙板粘合剂
公开(公告)号：US06300400B1
公开(公告)日：2001-10-09
申请号：US09061653
申请日：1998-04-17
申请人： Edward Stein , Steve Choi
发明人： Edward Stein , Steve Choi
IPC分类号： C08J510
CPC分类号： C09J131/04 , C08L1/00 , C08L2666/26 , C08L2666/54
摘要： A water-based wallboard adhesive including water, a binder, and a particulate filler is described. The adhesive can have an open time greater than about 5 minutes and a green strength sufficient to support a 4 foot by 8 foot wallboard on a wall frame without fasteners in the field of the wallboard within 15 minutes of applying the adhesive to the wallboard and wall frame.
摘要翻译：描述了包括水，粘合剂和颗粒填料的水基墙板粘合剂。粘合剂可以具有大于约5分钟的开放时间，并且具有足够的绿色强度，以在墙壁框架上支撑4英尺×8英尺的墙板，而在15分钟内将粘合剂施加到墙板和墙壁上帧。

9. 发明授权

US5982683A Enhanced method of testing semiconductor devices having nonvolatile elements 失效
标题翻译：具有非易失性元件的半导体器件测试的增强方法
公开(公告)号：US5982683A
公开(公告)日：1999-11-09
申请号：US046404
申请日：1998-03-23
申请人： James A. Watson , Fabiano Fontana , Jenny Chui , Steve Choi , Benjamin Lau
发明人： James A. Watson , Fabiano Fontana , Jenny Chui , Steve Choi , Benjamin Lau
IPC分类号： G11C29/10 , G11C7/00
CPC分类号： G11C29/10
摘要： An enhanced method of testing semiconductor devices having nonvolatile elements by determining regions of the semiconductor having differing orders of probability that a defect will occur. The enhanced method of testing includes testing of regions from the highest probability to the lowest probability of having a defect. Nonvolatile memory elements in the region being tested are placed in a high impedance state, bypass circuits in the region being tested are activated to bypass the nonvolatile memory elements that control the state of elements in the region being tested and test vectors are applied to the elements that are controlled by the bypassed nonvolatile memory elements. This procedure is repeated for the next untested region having the highest probability of having a defect until all regions have been tested.
摘要翻译：通过确定具有不同发生故障概率的半导体区域来测试具有非易失性元件的半导体器件的增强方法。增强的测试方法包括从最高概率到具有缺陷的最低概率的区域的测试。被测试区域中的非易失性存储元件被置于高阻抗状态，被测试区域中的旁路电路被激活以绕过控制待测区域中的元件状态的非易失性存储元件，测试矢量被应用于元件由旁路非易失性存储元件控制。对具有最大概率的缺陷的下一个未测试区域重复该过程，直到所有区域都已被测试为止。

10. 发明申请

US20090323415A1 FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL 有权
标题翻译：闪存存储器阵列系统，包括顶盖存储器单元
公开(公告)号：US20090323415A1
公开(公告)日：2009-12-31
申请号：US12507783
申请日：2009-07-22
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要翻译：存储器系统包括布置在扇区中的存储器单元。对应于扇区的解码器禁止具有缺陷顶门的存储单元。解码器可以包括用于禁用的低电压或高电压锁存器。包括顶栅处理算法。存储器系统可以包括动态顶栅耦合。包括具有顶栅处理的编程算法和波形。

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