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1. 发明申请

US20100214843A1 NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME 有权
标题翻译：非易失性存储器件和具有该存储器件的存储器系统
公开(公告)号：US20100214843A1
公开(公告)日：2010-08-26
申请号：US12639119
申请日：2009-12-16
申请人： Soo-Han Kim , Dae Han Kim
发明人： Soo-Han Kim , Dae Han Kim
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C16/26
摘要： A non-volatile memory device including a cell array having memory cells arranged at intersections of word lines and bit lines; an address decoder configured to select one of the word lines in response to an address; a write circuit configured to write program data in memory cells connected with the selected word line; and a control circuit configured to control the address decoder and the write circuit such that a plurality of band program (write) operations are sequentially executed during a write operation, wherein the control circuit is further configured to select each band write operation the optimal write condition of the next band write operation. A plurality of available write conditions are stored as trim information in a plurality of registers. The control circuit selects the register storing information for performing programming under the optimal write condition.
摘要翻译：一种非易失性存储器件，包括具有布置在字线和位线的交点处的存储单元的单元阵列; 地址解码器，被配置为响应于地址选择一条字线; 写入电路，被配置为将程序数据写入与所选择的字线连接的存储器单元中; 以及控制电路，被配置为控制地址解码器和写入电路，使得在写入操作期间顺序地执行多个频带程序（写入）操作，其中所述控制电路还被配置为选择每个频带写入操作的最佳写入条件的下一个频带写操作。多个可用写入条件作为修剪信息存储在多个寄存器中。控制电路选择用于在最佳写入条件下进行编程的寄存器存储信息。

2. 发明授权

US08238160B2 Nonvolatile memory device and memory system having the same 有权
标题翻译：非易失性存储器件和具有相同的存储器系统
公开(公告)号：US08238160B2
公开(公告)日：2012-08-07
申请号：US12639119
申请日：2009-12-16
申请人： Soo-Han Kim , Dae Han Kim
发明人： Soo-Han Kim , Dae Han Kim
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C16/26
摘要： A non-volatile memory device including a cell array having memory cells arranged at intersections of word lines and bit lines; an address decoder configured to select one of the word lines in response to an address; a write circuit configured to write program data in memory cells connected with the selected word line; and a control circuit configured to control the address decoder and the write circuit such that a plurality of band program (write) operations are sequentially executed during a write operation, wherein the control circuit is further configured to select each band write operation the optimal write condition of the next band write operation. A plurality of available write conditions are stored as trim information in a plurality of registers. The control circuit selects the register storing information for performing programming under the optimal write condition.
摘要翻译：一种非易失性存储器件，包括具有布置在字线和位线的交点处的存储单元的单元阵列; 地址解码器，被配置为响应于地址选择一条字线; 写入电路，被配置为将程序数据写入与所选择的字线连接的存储器单元中; 以及控制电路，被配置为控制地址解码器和写入电路，使得在写入操作期间顺序地执行多个频带程序（写入）操作，其中所述控制电路还被配置为选择每个频带写入操作的最佳写入条件的下一个频带写操作。多个可用写入条件作为修剪信息存储在多个寄存器中。控制电路选择用于在最佳写入条件下进行编程的寄存器存储信息。

3. 发明授权

US07349263B2 Circuit and method for adaptive incremental step-pulse programming in a flash memory device 有权
标题翻译：闪存器件中自适应增量步进脉冲编程的电路和方法
公开(公告)号：US07349263B2
公开(公告)日：2008-03-25
申请号：US11381140
申请日：2006-05-02
申请人： Soo-Han Kim , Jae-Yong Jeong
发明人： Soo-Han Kim , Jae-Yong Jeong
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/3454 , G11C16/3459
摘要： Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has been verified as a “passed” memory cell. The nonvolatile memory device includes an array of nonvolatile memory cells and a control circuit, which is electrically coupled to the array of nonvolatile memory cells. The control circuit is configured to perform a plurality of memory programming operations (P) by driving a selected word line in the array with a first stair step sequence of program voltages having first step height (e.g., ΔV1) and then, in response to verifying that at least one of the memory cells coupled to the selected word line is a passed memory cell, driving the selected word line with a second stair step sequence of program voltages having a second step height (e.g., ΔV2) lower than the first step height.
摘要翻译：非易失性存储器件支持编程和验证操作，以改善程序存储单元内的阈值电压分布。一旦将经历编程的多个存储器单元中的至少一个已经被验证为“传递”的存储器单元，则通过减小编程电压步长的大小并增加验证操作的持续时间来实现这种改进。非易失性存储器件包括非易失性存储器单元的阵列和电耦合到非易失性存储单元阵列的控制电路。控制电路被配置为通过以具有第一台阶高度（例如，DeltaV 1）的编程电压的第一阶梯顺序驱动阵列中的选定字线来执行多个存储器编程操作（P），然后响应于验证耦合到所选择的字线的存储器单元中的至少一个是经过的存储单元，用具有比第一个字线低的第二阶梯高度（例如，DeltaV 2）的编程电压的第二阶梯顺序驱动所选择的字线步高。

4. 发明授权

US07489565B2 Flash memory device including multi-buffer block 失效
标题翻译：闪存设备包括多缓冲块
公开(公告)号：US07489565B2
公开(公告)日：2009-02-10
申请号：US11762797
申请日：2007-06-14
申请人： Ji-Ho Cho , Soo-Han Kim , June-Hong Park
发明人： Ji-Ho Cho , Soo-Han Kim , June-Hong Park
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/1006 , G11C7/1084 , G11C7/1087 , G11C7/1096 , G11C8/06 , G11C8/08 , G11C8/10 , G11C16/10 , G11C2207/104 , G11C2216/14
摘要： A flash memory device includes a memory cell array and a multi-buffer block which temporarily stores program data that are to be stored in the memory cell array, wherein the multi-buffer block includes a plurality of buffer circuits which store at least 2-word data, respectively. Each of the buffer circuits includes a plurality of registers which store two corresponding data bits among the at least 2-word data, respectively and scan logics corresponding to the registers, respectively, which scan a number of program data of a first word data among the at least 2-word data during a first scan interval, and which scan a number of program data of a second word data among the at least 2-word data based on the number of the program data of the first word data during a second scan interval.
摘要翻译：闪速存储器件包括存储单元阵列和临时存储要存储在存储单元阵列中的程序数据的多缓冲块，其中多缓冲块包括存储至少2个字的多个缓冲电路数据。每个缓冲电路包括多个寄存器，分别在至少2个字数据中存储两个相应的数据位，分别扫描对应于寄存器的逻辑，扫描逻辑数据中的第一个字数据的多个节目数据在第一扫描间隔期间的至少2字数据，并且在第二扫描期间，基于第一字数据的节目数据的数目，扫描至少2个字数据中的第二字数据的数目的数目间隔。

5. 发明申请

US20080137435A1 Flash memory devices that support incremental step-pulse programming using nonuniform verify time intervals 有权
标题翻译：使用非均匀验证时间间隔支持增量式步进脉冲编程的闪存设备
公开(公告)号：US20080137435A1
公开(公告)日：2008-06-12
申请号：US12031422
申请日：2008-02-14
申请人： Soo-Han Kim , Jae-Yong Jeong
发明人： Soo-Han Kim , Jae-Yong Jeong
IPC分类号： G11C16/06
CPC分类号： G11C16/12 , G11C16/3454 , G11C16/3459
摘要： Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has been verified as a “passed” memory cell. The nonvolatile memory device includes an array of nonvolatile memory cells and a control circuit, which is electrically coupled to the array of nonvolatile memory cells. The control circuit is configured to perform a plurality of memory programming operations (P) by driving a selected word line in the array with a first stair step sequence of program voltages having first step height (e.g., ΔV1) and then, in response to verifying that at least one of the memory cells coupled to the selected word line is a passed memory cell, driving the selected word line with a second stair step sequence of program voltages having a second step height (e.g., ΔV2) lower than the first step height.
摘要翻译：非易失性存储器件支持编程和验证操作，以改善程序存储单元内的阈值电压分布。一旦将经历编程的多个存储器单元中的至少一个已经被验证为“传递”的存储器单元，则通过减小编程电压步长的大小并增加验证操作的持续时间来实现这种改进。非易失性存储器件包括非易失性存储器单元的阵列和电耦合到非易失性存储单元阵列的控制电路。控制电路被配置为通过以具有第一台阶高度（例如，DeltaV 1）的编程电压的第一阶梯顺序驱动阵列中的选定字线来执行多个存储器编程操作（P），然后响应于验证耦合到所选择的字线的存储器单元中的至少一个是经过的存储单元，用具有低于第一个字线的第二阶梯高度（例如，DeltaV 2）的编程电压的第二阶梯顺序驱动所选择的字线步高。

6. 发明授权

US07339651B2 Exposure equipment and related control method 失效
标题翻译：曝光设备及相关控制方法
公开(公告)号：US07339651B2
公开(公告)日：2008-03-04
申请号：US11213849
申请日：2005-08-30
申请人： Soo-Han Kim
发明人： Soo-Han Kim
IPC分类号： G03B27/42 , G03B27/32 , G01B11/00
CPC分类号： G03B27/68 , G03F7/70633 , G03F7/70716 , G03F7/7085
摘要： Exposure equipment adapted for use in the manufacture of semiconductor devices and a related control are disclosed. A wafer stage in the exposure equipment comprises an image sensor adapted to detect patterned light from the reticle. Image data corresponding to the detected patterned light is compared to reference image data to verify a state of overlay mismatch of reticle pattern accuracy prior to wafer exposure.
摘要翻译：公开了适用于制造半导体器件和相关控制的曝光设备。曝光设备中的晶片台包括适于检测来自掩模版的图案光的图像传感器。对应于检测到的图案化光的图像数据与参考图像数据进行比较，以验证在晶片曝光之前的掩模版图形精度的叠加失配的状态。

7. 发明申请

US20060072086A1 Exposure equipment and related control method 失效
标题翻译：曝光设备及相关控制方法
公开(公告)号：US20060072086A1
公开(公告)日：2006-04-06
申请号：US11213849
申请日：2005-08-30
申请人： Soo-Han Kim
发明人： Soo-Han Kim
IPC分类号： G03B27/68
CPC分类号： G03B27/68 , G03F7/70633 , G03F7/70716 , G03F7/7085
摘要： Exposure equipment adapted for use in the manufacture of semiconductor devices and a related control are disclosed. A wafer stage in the exposure equipment comprises an image sensor adapted to detect patterned light from the reticle. Image data corresponding to the detected patterned light is compared to reference image data to verify a state of overlay mismatch of reticle pattern accuracy prior to wafer exposure.
摘要翻译：公开了适用于制造半导体器件和相关控制的曝光设备。曝光设备中的晶片台包括适于检测来自掩模版的图案光的图像传感器。对应于检测到的图案化光的图像数据与参考图像数据进行比较，以验证在晶片曝光之前的掩模版图形精度的叠加失配的状态。

8. 发明授权

US07599219B2 Flash memory devices that support incremental step-pulse programming using nonuniform verify time intervals 有权
标题翻译：使用非均匀验证时间间隔支持增量式步进脉冲编程的闪存设备
公开(公告)号：US07599219B2
公开(公告)日：2009-10-06
申请号：US12031422
申请日：2008-02-14
申请人： Soo-Han Kim , Jae-Yong Jeong
发明人： Soo-Han Kim , Jae-Yong Jeong
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/3454 , G11C16/3459
摘要： Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has been verified as a “passed” memory cell. The nonvolatile memory device includes an array of nonvolatile memory cells and a control circuit, which is electrically coupled to the array of nonvolatile memory cells. The control circuit is configured to perform a plurality of memory programming operations (P) by driving a selected word line in the array with a first stair step sequence of program voltages having first step height (e.g., ΔV1) and then, in response to verifying that at least one of the memory cells coupled to the selected word line is a passed memory cell, driving the selected word line with a second stair step sequence of program voltages having a second step height (e.g., ΔV2) lower than the first step height.
摘要翻译：非易失性存储器件支持编程和验证操作，以改善程序存储单元内的阈值电压分布。一旦将经历编程的多个存储器单元中的至少一个已经被验证为“传递”的存储器单元，则通过减小编程电压步长的大小并增加验证操作的持续时间来实现这种改进。非易失性存储器件包括非易失性存储器单元的阵列和电耦合到非易失性存储单元阵列的控制电路。控制电路被配置为通过用具有第一级高度（例如，DeltaV1）的编程电压的第一阶梯级序列驱动阵列中的选定字线，然后响应于验证，执行多个存储器编程操作（P）耦合到所选择的字线的存储单元中的至少一个是经过的存储单元，用具有低于第一台阶高度（例如，DeltaV2）的编程电压的第二阶梯顺序驱动所选择的字线。

9. 发明申请

US20060291290A1 Circuit and Method for Adaptive Incremental Step-Pulse Programming in a Flash Memory Device 有权
标题翻译：闪存设备中自适应增量步进脉冲编程的电路和方法
公开(公告)号：US20060291290A1
公开(公告)日：2006-12-28
申请号：US11381140
申请日：2006-05-02
申请人： Soo-Han Kim , Jae-Yong Jeong
发明人： Soo-Han Kim , Jae-Yong Jeong
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/3454 , G11C16/3459
摘要： Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has been verified as a “passed” memory cell. The nonvolatile memory device includes an array of nonvolatile memory cells and a control circuit, which is electrically coupled to the array of nonvolatile memory cells. The control circuit is configured to perform a plurality of memory programming operations (P) by driving a selected word line in the array with a first stair step sequence of program voltages having first step height (e.g., ΔV1) and then, in response to verifying that at least one of the memory cells coupled to the selected word line is a passed memory cell, driving the selected word line with a second stair step sequence of program voltages having a second step height (e.g., ΔV2) lower than the first step height.
摘要翻译：非易失性存储器件支持编程和验证操作，以改善程序存储单元内的阈值电压分布。一旦将经历编程的多个存储器单元中的至少一个已经被验证为“传递”的存储器单元，则通过减小编程电压步长的大小并增加验证操作的持续时间来实现这种改进。非易失性存储器件包括非易失性存储器单元的阵列和电耦合到非易失性存储单元阵列的控制电路。控制电路被配置为通过以具有第一台阶高度（例如，DeltaV 1）的编程电压的第一阶梯顺序驱动阵列中的选定字线来执行多个存储器编程操作（P），然后响应于验证耦合到所选择的字线的存储器单元中的至少一个是经过的存储单元，用具有低于第一个字线的第二阶梯高度（例如，DeltaV 2）的编程电压的第二阶梯顺序驱动所选择的字线步高。

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