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1. 发明申请

US20060163613A1 Layout structure for sub word line drivers and method thereof 有权
标题翻译：子字线驱动器的布局结构及其方法
公开(公告)号：US20060163613A1
公开(公告)日：2006-07-27
申请号：US11336831
申请日：2006-01-23
申请人： Soo-Bong Chang , In-Chul Jeong , Jun-Hyung Kim , Seung-Min Oh , Jung-Hwa Lee
发明人： Soo-Bong Chang , In-Chul Jeong , Jun-Hyung Kim , Seung-Min Oh , Jung-Hwa Lee
IPC分类号： H01L27/10
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/11898
摘要： A layout structure for sub word line drivers and method thereof. The example layout structure may include at least one N-channel transistor arrangement having a cross sectional width and a cross sectional length, the N-channel transistor arrangement oriented such that the cross sectional length extends along a first direction, the first direction oriented along a sub word line driver from a first sub array block to a second sub array block. The example method may arrange the at least one N-channel transistor between the first and second sub array blocks.
摘要翻译：子字线驱动器的布局结构及其方法。示例性布局结构可以包括具有横截面宽度和横截面长度的至少一个N沟道晶体管布置，N沟道晶体管布置方向使得横截面长度沿着第一方向延伸，第一方向沿着第一方向子字线驱动器从第一子阵列块到第二子阵列块。该示例性方法可以在第一和第二子阵列块之间布置至少一个N沟道晶体管。

2. 发明授权

US07359280B2 Layout structure for sub word line drivers and method thereof 有权
标题翻译：子字线驱动器的布局结构及其方法
公开(公告)号：US07359280B2
公开(公告)日：2008-04-15
申请号：US11336831
申请日：2006-01-23
申请人： Soo-Bong Chang , In-Chul Jeong , Jun-Hyung Kim , Seung-Min Oh , Jung-Hwa Lee
发明人： Soo-Bong Chang , In-Chul Jeong , Jun-Hyung Kim , Seung-Min Oh , Jung-Hwa Lee
IPC分类号： G11C8/00
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/11898
摘要： A layout structure for sub word line drivers and method thereof. The example layout structure may include at least one N-channel transistor arrangement having a cross sectional width and a cross sectional length, the N-channel transistor arrangement oriented such that the cross sectional length extends along a first direction, the first direction oriented along a sub word line driver from a first sub array block to a second sub array block. The example method may arrange the at least one N-channel transistor between the first and second sub array blocks.
摘要翻译：子字线驱动器的布局结构及其方法。示例性布局结构可以包括具有横截面宽度和横截面长度的至少一个N沟道晶体管布置，N沟道晶体管布置方向使得横截面长度沿着第一方向延伸，第一方向沿着第一方向子字线驱动器从第一子阵列块到第二子阵列块。该示例性方法可以在第一和第二子阵列块之间布置至少一个N沟道晶体管。

3. 发明授权

US06847536B1 Semiconductor memory device having structure for preventing level of boosting voltage applied to a node from dropping and method of forming the same 失效
标题翻译：具有防止施加到节点的升压电压下降的结构的半导体存储器件及其形成方法
公开(公告)号：US06847536B1
公开(公告)日：2005-01-25
申请号：US10889495
申请日：2004-07-12
申请人： Jung-Hwa Lee , Soo-Bong Chang
发明人： Jung-Hwa Lee , Soo-Bong Chang
IPC分类号： H01L27/04 , G11C5/02 , G11C5/06 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10897 , G11C5/025 , G11C5/063 , H01L27/105 , H01L27/10814
摘要： A semiconductor memory device includes a column decoder, a row decoder, a memory cell array block, and a sense amplifier block. The sense amplifier block is disposed adjacent to the memory cell array block. The column decoder is disposed at one side of the memory cell array block, and the row decoder is disposed at another side of the memory cell array block. First output lines of the row decoder pass over the sense amplifier block and are formed of first metal layers. Second output lines of the row decoder pass over the memory cell array block and are formed of second metal layers. Output lines of the column decoder pass over the sense amplifier block and the memory cell array block. Portions of the output lines of the column decoder passing over the sense amplifier block are formed of the second metal layers and portions of the output lines of the column decoder that pass over the memory cell array block are formed of the first metal layers.
摘要翻译：半导体存储器件包括列解码器，行解码器，存储单元阵列块和读出放大器块。读出放大器块被布置成与存储单元阵列块相邻。列解码器设置在存储单元阵列块的一侧，行解码器设置在存储单元阵列块的另一侧。行解码器的第一输出行通过读出放大器块，并由第一金属层形成。行解码器的第二输出行通过存储单元阵列块并且由第二金属层形成。列解码器的输出行通过读出放大器块和存储单元阵列块。通过读出放大器块的列解码器的输出行的部分由第二金属层形成，并且通过存储单元阵列块的列解码器的输出线的部分由第一金属层形成。

4. 发明申请

US20050013152A1 SEMICONDUCTOR MEMORY DEVICE HAVING STRUCTURE FOR PREVENTING LEVEL OF BOOSTING VOLTAGE APPLIED TO A NODE FROM DROPPING AND METHOD OF FORMING THE SAME 失效
标题翻译：具有用于防止施加于节点上的升压电压的结构的半导体存储器件及其形成方法
公开(公告)号：US20050013152A1
公开(公告)日：2005-01-20
申请号：US10889495
申请日：2004-07-12
申请人： Jung-Hwa Lee , Soo-Bong Chang
发明人： Jung-Hwa Lee , Soo-Bong Chang
IPC分类号： H01L27/04 , G11C5/02 , G11C5/06 , H01L27/105 , H01L27/108 , G11C8/00
CPC分类号： H01L27/10897 , G11C5/025 , G11C5/063 , H01L27/105 , H01L27/10814
摘要： A semiconductor memory device includes a column decoder, a row decoder, a memory cell array block, and a sense amplifier block. The sense amplifier block is disposed adjacent to the memory cell array block. The column decoder is disposed at one side of the memory cell array block, and the row decoder is disposed at another side of the memory cell array block. First output lines of the row decoder pass over the sense amplifier block and are formed of first metal layers. Second output lines of the row decoder pass over the memory cell array block and are formed of second metal layers. Output lines of the column decoder pass over the sense amplifier block and the memory cell array block. Portions of the output lines of the column decoder passing over the sense amplifier block are formed of the second metal layers and portions of the output lines of the column decoder that pass over the memory cell array block are formed of the first metal layers.
摘要翻译：半导体存储器件包括列解码器，行解码器，存储单元阵列块和读出放大器块。读出放大器块被布置成与存储单元阵列块相邻。列解码器设置在存储单元阵列块的一侧，行解码器设置在存储单元阵列块的另一侧。行解码器的第一输出行通过读出放大器块，并由第一金属层形成。行解码器的第二输出行通过存储单元阵列块并且由第二金属层形成。列解码器的输出行通过读出放大器块和存储单元阵列块。通过读出放大器块的列解码器的输出行的部分由第二金属层形成，并且通过存储单元阵列块的列解码器的输出线的部分由第一金属层形成。

5. 发明授权

US07075849B2 Semiconductor memory device and layout method thereof 失效
标题翻译：半导体存储器件及其布局方法
公开(公告)号：US07075849B2
公开(公告)日：2006-07-11
申请号：US10786855
申请日：2004-02-24
申请人： Soo-Bong Chang , Jung-Hwa Lee , Chi-Wook Kim , Byong-Mo Moon
发明人： Soo-Bong Chang , Jung-Hwa Lee , Chi-Wook Kim , Byong-Mo Moon
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C5/14
摘要： Embodiments of the invention provide drivers from active internal voltage generating circuits on both sides of the internal voltage generating lines, therefore a voltage level of the internal voltage generating lines can quickly and uniformly reach a desired internal voltage level. Other embodiments of the invention are described in the claims.
摘要翻译：本发明的实施例提供了内部电压发生线两侧的有源内部电压产生电路的驱动器，因此内部电压发生线的电压电平可以快速均匀地达到期望的内部电压电平。在权利要求中描述了本发明的其它实施例。

6. 发明授权

US07462912B2 Semiconductor memory device having power decoupling capacitor 有权
标题翻译：具有电源去耦电容器的半导体存储器件
公开(公告)号：US07462912B2
公开(公告)日：2008-12-09
申请号：US11361580
申请日：2006-02-24
申请人： Soon-Hong Ahn , Jung-Hwa Lee
发明人： Soon-Hong Ahn , Jung-Hwa Lee
IPC分类号： H01L29/76 , H01L29/00
CPC分类号： H01L27/0207 , H01L27/10894
摘要： Provided is a semiconductor memory device using a layout scheme where a bottom conductive layer in a peripheral circuit region, which is simultaneously formed with a self-align contact, is connected to one electrode of a power decoupling capacitor. Predetermined capacitors selected among a plurality of capacitors are connected to each other in parallel by using a conductive layer that is simultaneously formed with the self-align contact in a cell array region. Herein, the conductive layer and the self-align contact may be made of the same material. It is possible to embody the decoupling capacitor of a single stage cell type by connecting the conductive layer to a top interconnection layer. In addition, other embodiments implement the decoupling capacitor in a two-stage cell type by connecting a plurality of decoupling capacitors in series by means of the conductive layer in the peripheral circuit region.
摘要翻译：提供了一种使用布局方案的半导体存储器件，其中同时形成有自对准接触的外围电路区域中的底部导电层连接到功率去耦电容器的一个电极。通过使用与单元阵列区域中的自对准接触同时形成的导电层，并联地将多个电容器中选择的预定电容器并联连接。这里，导电层和自对准接触可以由相同的材料制成。通过将导电层连接到顶部互连层，可以体现单级电池类型的去耦电容器。此外，其他实施例通过在外围电路区域中通过导电层连接多个解耦电容器来实现两级单元类型的去耦电容器。

7. 发明申请

US20070153612A1 Circuit and method of generating a boosted voltage in a semiconductor memory device 失效
标题翻译：在半导体存储器件中产生升压电压的电路和方法
公开(公告)号：US20070153612A1
公开(公告)日：2007-07-05
申请号：US11640857
申请日：2006-12-19
申请人： Jae-Young Lee , Hong-Jun Lee , Jung-Hwa Lee
发明人： Jae-Young Lee , Hong-Jun Lee , Jung-Hwa Lee
IPC分类号： G11C5/14
CPC分类号： G11C5/145
摘要： A circuit generates a boosted voltage in a semiconductor memory device, where the semiconductor memory device includes a memory cell array having a plurality of non-edge sub-arrays and at least one edge sub-array. The circuit includes a plurality of boosted voltage generators configured to generate a boosted voltage having different current driving capabilities to activate the non-edge sub-arrays and the edge sub-arrays and to supply the boosted voltage to the memory cell array.
摘要翻译：电路在半导体存储器件中产生升压电压，其中半导体存储器件包括具有多个非边缘子阵列和至少一个边缘子阵列的存储单元阵列。该电路包括多个升压电压发生器，其被配置为产生具有不同电流驱动能力的升压电压以激活非边缘子阵列和边缘子阵列，并将升压电压提供给存储单元阵列。

8. 发明申请

US20060289932A1 Semiconductor memory device having power decoupling capacitor 有权
标题翻译：具有电源去耦电容器的半导体存储器件
公开(公告)号：US20060289932A1
公开(公告)日：2006-12-28
申请号：US11361580
申请日：2006-02-24
申请人： Soon-Hong Ahn , Jung-Hwa Lee
发明人： Soon-Hong Ahn , Jung-Hwa Lee
IPC分类号： H01L29/76
CPC分类号： H01L27/0207 , H01L27/10894
摘要： Provided is a semiconductor memory device using a layout scheme where a bottom conductive layer in a peripheral circuit region, which is simultaneously formed with a self-align contact, is connected to one electrode of a power decoupling capacitor. Predetermined capacitors selected among a plurality of capacitors are connected to each other in parallel by using a conductive layer that is simultaneously formed with the self-align contact in a cell array region. Herein, the conductive layer and the self-align contact may be made of the same material. It is possible to embody the decoupling capacitor of a single stage cell type by connecting the conductive layer to a top interconnection layer. In addition, other embodiments implement the decoupling capacitor in a two-stage cell type by connecting a plurality of decoupling capacitors in series by means of the conductive layer in the peripheral circuit region.
摘要翻译：提供了一种使用布局方案的半导体存储器件，其中同时形成有自对准接触的外围电路区域中的底部导电层连接到功率去耦电容器的一个电极。通过使用与单元阵列区域中的自对准接触同时形成的导电层，并联地将多个电容器中选择的预定电容器并联连接。这里，导电层和自对准接触可以由相同的材料制成。通过将导电层连接到顶部互连层，可以体现单级电池类型的去耦电容器。此外，其他实施例通过在外围电路区域中通过导电层连接多个解耦电容器来实现两级单元类型的去耦电容器。

9. 发明授权

US5657265A Semiconductor memory device having circuit array structure for fast operation 失效
标题翻译：具有用于快速操作的电路阵列结构的半导体存储器件
公开(公告)号：US5657265A
公开(公告)日：1997-08-12
申请号：US673001
申请日：1996-07-01
申请人： Jei-Hwan Yoo , Jung-Hwa Lee
发明人： Jei-Hwan Yoo , Jung-Hwa Lee
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C11/4096 , H01L21/8242 , H01L27/108 , G11C5/06
CPC分类号： G11C7/10 , G11C11/4096
摘要： A semiconductor memory device includes at least four memory cell array blocks, each having an array of memory cells, row and column decoders for selecting a memory cell designated by a row and column address, an I/O line for inputting/outputting data of the memory cell array block, and an I/O driver connected to the I/O line for selectively driving data to/from a selected memory cell. A first data line transmits the data, being connected between the I/O driver of one memory cell array block and the I/O driver of another memory cell array block oppositely arranged with respect to a central portion of the semiconductor memory device. A second data line transmits the data by connecting the first data lines of at least two memory cell array blocks disposed adjacent to each other. A data sense amplifier, connected to the second data line, senses and amplifies the data, and a data output unit, connected to the data sense amplifier, outputs the amplified data to an external lead frame. Therefore, the present invention has an advantage in that a relatively small layout area in required and a relatively low amount of power is consumed.
摘要翻译：半导体存储器件包括至少四个存储单元阵列块，每个存储单元阵列块具有存储单元阵列，用于选择由行和列地址指定的存储单元的行和列解码器，用于输入/输出数据的数据的I / O线存储单元阵列块和连接到I / O线的I / O驱动器，用于选择性地将数据传送到所选择的存储单元。第一数据线传送连接在一个存储单元阵列块的I / O驱动器和相对于半导体存储器件的中心部分相对布置的另一存储单元阵列块的I / O驱动器之间的数据。第二数据线通过连接彼此相邻布置的至少两个存储单元阵列块的第一数据线来发送数据。连接到第二数据线的数据读出放大器感测并放大数据，连接到数据读出放大器的数据输出单元将放大的数据输出到外部引线框。因此，本发明的优点是消耗了所需的相对小的布局面积和相对低的功率。

10. 发明授权

US08295111B2 Semiconductor memory device comprising sensing circuits with adjacent column selectors 有权
标题翻译：半导体存储器件包括具有相邻列选择器的感测电路
公开(公告)号：US08295111B2
公开(公告)日：2012-10-23
申请号：US12894246
申请日：2010-09-30
申请人： Jae-Young Lee , Jung-Hwa Lee , Bong-Jin Kang
发明人： Jae-Young Lee , Jung-Hwa Lee , Bong-Jin Kang
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： A semiconductor memory device comprises a substrate comprising a first cell array region, a first sense circuit region, a second sense circuit region, and a second cell array region that are arranged in order from a first side to a second side. First and second bit lines are coupled to a plurality of memory cells in the first cell array region, and first and second complementary bit lines are coupled to a plurality of memory cells in the second cell array region. A first column selector is formed in the first sense circuit region and is coupled to the first bit line and the first complementary bit line. A second column selector is formed in the second sense circuit region and is coupled to the second bit line and the second complementary bit line. The first column selector and the second column selector are formed directly adjacent to each other.
摘要翻译：一种半导体存储器件，包括一个衬底，该衬底包括从第一侧到第二侧依次布置的第一单元阵列区，第一感测电路区，第二感测电路区和第二单元阵列区。第一和第二位线耦合到第一单元阵列区域中的多个存储单元，并且第一和第二互补位线耦合到第二单元阵列区域中的多个存储单元。第一列选择器形成在第一感测电路区域中，并且耦合到第一位线和第一互补位线。第二列选择器形成在第二感测电路区域中，并且耦合到第二位线和第二互补位线。第一列选择器和第二列选择器彼此直接相邻地形成。

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