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1. 发明申请

US20130234220A1 SOLID-STATE IMAGING DEVICE AND IMAGING APPARATUS 有权
标题翻译：固态成像装置和成像装置
公开(公告)号：US20130234220A1
公开(公告)日：2013-09-12
申请号：US13756124
申请日：2013-01-31
申请人： SONY CORPORATION
发明人： Hiroshi Tayanaka , Susumu Ooki , Junichi Furukawa , Fumiaki Okazaki
IPC分类号： H01L31/0232
CPC分类号： H01L31/0232 , H04N5/2254 , H04N5/37457
摘要： An imaging device includes a basic cell having two or more the pixels that share floating diffusion. The imaging device also includes a transistor shared by the two or more pixels in the basic cell and arranged on the outside of the two or more pixels. The imaging device further includes a light receiving unit connected to the floating diffusion shared by the pixels in the basic cell through a transfer gate. In the imaging device, on-chip lenses are arranged substantially at regular intervals. Also, an optical waveguide is formed so that the position thereof in the surface of the solid-state imaging device is located at a position shifted from the center of the light receiving unit to the transistor and in the inside of the light receiving unit and the inside of the on-chip lens.
摘要翻译：成像装置包括具有两个或更多个共享浮动扩散的像素的基本单元。成像装置还包括由基本单元中的两个或更多像素共享的并且布置在两个或更多个像素的外侧上的晶体管。成像装置还包括光接收单元，其通过传送门连接到基本单元中的像素共享的浮动扩散。在成像装置中，片上透镜基本上以规则的间隔布置。此外，形成光波导，使得其在固态成像装置的表面中的位置位于从光接收单元的中心偏移到晶体管和光接收单元的内部的位置，并且片内镜头内。

2. 发明授权

US11289581B2 Method for manufacturing insulated gate field effect transistor 有权
公开(公告)号：US11289581B2
公开(公告)日：2022-03-29
申请号：US16668867
申请日：2019-10-30
申请人： Sony Corporation
发明人： Fumiaki Okazaki
IPC分类号： H01L29/49 , H01L21/28 , H01L21/768 , H01L29/51 , H01L29/66 , H01L29/78
摘要： An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer on the first interlayer insulating layer.

3. 发明授权

US10014384B2 Method for manufacturing insulated gate field effect transistor 有权
公开(公告)号：US10014384B2
公开(公告)日：2018-07-03
申请号：US14560123
申请日：2014-12-04
申请人： Sony Corporation
发明人： Fumiaki Okazaki
IPC分类号： H01L29/49 , H01L21/28 , H01L21/768 , H01L29/51 , H01L29/66 , H01L29/78
CPC分类号： H01L29/4983 , H01L21/28097 , H01L21/28194 , H01L21/76801 , H01L21/76832 , H01L29/4975 , H01L29/517 , H01L29/66545 , H01L29/6659 , H01L29/66772 , H01L29/78 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer configured to be formed on the first interlayer insulating layer.

4. 发明申请

US20200066863A1 METHOD FOR MANUFACTURING INSULATED GATE FIELD EFFECT TRANSISTOR 审中-公开
公开(公告)号：US20200066863A1
公开(公告)日：2020-02-27
申请号：US16668867
申请日：2019-10-30
申请人： Sony Corporation
发明人： Fumiaki Okazaki
IPC分类号： H01L29/49 , H01L21/28 , H01L21/768 , H01L29/51 , H01L29/66 , H01L29/78
摘要： An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer on the first interlayer insulating layer.

5. 发明申请

US20150084105A1 METHOD FOR MANUFACTURING INSULATED GATE FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：制造绝缘栅场效应晶体管的方法
公开(公告)号：US20150084105A1
公开(公告)日：2015-03-26
申请号：US14560123
申请日：2014-12-04
申请人： Sony Corporation
发明人： Fumiaki Okazaki
IPC分类号： H01L29/49 , H01L29/78
CPC分类号： H01L29/4983 , H01L21/28097 , H01L21/28194 , H01L21/76801 , H01L21/76832 , H01L29/4975 , H01L29/517 , H01L29/66545 , H01L29/6659 , H01L29/66772 , H01L29/78 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer configured to be formed on the first interlayer insulating layer.
摘要翻译：一种绝缘栅场效应晶体管，其具有（a）具有源极/漏极区域的基极，沟道形成区域，形成在沟道形成区域上的栅极绝缘膜，覆盖源极/漏极区域的绝缘层，以及栅极形成开口设置在所述沟道形成区域上方的所述绝缘层的部分部分中; （b）通过在栅电极形成开口中埋入导电材料层而形成的栅电极; （c）在所述绝缘层和所述栅电极上形成并且不含氧原子作为构成元素的第一层间绝缘层; 以及（d）构造成形成在所述第一层间绝缘层上的第二层间绝缘层。

6. 发明授权

US10505008B2 Method for manufacturing insulated gate field effect transistor 有权
公开(公告)号：US10505008B2
公开(公告)日：2019-12-10
申请号：US15982095
申请日：2018-05-17
申请人： Sony Corporation
发明人： Fumiaki Okazaki
IPC分类号： H01L29/49 , H01L21/28 , H01L21/768 , H01L29/51 , H01L29/66 , H01L29/78
CPC分类号： H01L29/4983 , H01L21/28097 , H01L21/28194 , H01L21/76801 , H01L21/76832 , H01L29/4975 , H01L29/517 , H01L29/6659 , H01L29/66545 , H01L29/78 , H01L29/7833 , H01L29/7843 , H01L29/66772 , H01L2924/0002 , H01L2924/0002 , H01L2924/00
摘要： An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer on the first interlayer insulating layer.

7. 发明申请

US20180269300A1 METHOD FOR MANUFACTURING INSULATED GATE FIELD EFFECT TRANSISTOR 审中-公开
公开(公告)号：US20180269300A1
公开(公告)日：2018-09-20
申请号：US15982095
申请日：2018-05-17
申请人： Sony Corporation
发明人： Fumiaki Okazaki
IPC分类号： H01L29/49 , H01L21/28 , H01L29/78
CPC分类号： H01L29/4983 , H01L21/28097 , H01L21/28194 , H01L21/76801 , H01L21/76832 , H01L29/4975 , H01L29/517 , H01L29/66545 , H01L29/6659 , H01L29/66772 , H01L29/78 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer on the first interlayer insulating layer.

8. 发明授权

US08817164B2 Solid-State imaging device and imaging apparatus having offset optical waveguides 有权
标题翻译：具有偏移光波导的固态成像装置和成像装置
公开(公告)号：US08817164B2
公开(公告)日：2014-08-26
申请号：US13756124
申请日：2013-01-31
申请人： Sony Corporation
发明人： Hiroshi Tayanaka , Susumu Ooki , Junichi Furukawa , Fumiaki Okazaki
IPC分类号： H04N5/225 , H04N3/14 , H04N5/335
CPC分类号： H01L31/0232 , H04N5/2254 , H04N5/37457
摘要： An imaging device includes a basic cell having two or more the pixels that share floating diffusion. The imaging device also includes a transistor shared by the two or more pixels in the basic cell and arranged on the outside of the two or more pixels. The imaging device further includes a light receiving unit connected to the floating diffusion shared by the pixels in the basic cell through a transfer gate. In the imaging device, on-chip lenses are arranged substantially at regular intervals. Also, an optical waveguide is formed so that the position thereof in the surface of the solid-state imaging device is located at a position shifted from the center of the light receiving unit to the transistor and in the inside of the light receiving unit and the inside of the on-chip lens.
摘要翻译：成像装置包括具有两个或更多个共享浮动扩散的像素的基本单元。成像装置还包括由基本单元中的两个或更多像素共享的并且布置在两个或更多个像素的外侧上的晶体管。成像装置还包括光接收单元，其通过传送门连接到基本单元中的像素共享的浮动扩散。在成像装置中，片上透镜基本上以规则的间隔布置。此外，形成光波导，使得其在固态成像装置的表面中的位置位于从光接收单元的中心偏移到晶体管和光接收单元的内部的位置，并且片内镜头内。

9. 发明申请

US20130292748A1 METHOD FOR MANUFACTURING INSULATED GATE FIELD EFFECT TRANSISTOR 审中-公开
公开(公告)号：US20130292748A1
公开(公告)日：2013-11-07
申请号：US13916002
申请日：2013-06-12
申请人： Sony Corporation
发明人： Fumiaki Okazaki
IPC分类号： H01L29/78
CPC分类号： H01L29/4983 , H01L21/28097 , H01L21/28194 , H01L21/76801 , H01L21/76832 , H01L29/4975 , H01L29/517 , H01L29/66545 , H01L29/6659 , H01L29/66772 , H01L29/78 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer configured to be formed on the first interlayer insulating layer.

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