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1. 发明申请

US20090072344A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090072344A1
公开(公告)日：2009-03-19
申请号：US11966421
申请日：2007-12-28
申请人： Song Hyeuk Im
发明人： Song Hyeuk Im
IPC分类号： H01L27/00 , H01L21/76
CPC分类号： H01L21/823481 , H01L21/823437 , H01L21/84 , H01L27/1052 , H01L27/10876 , H01L27/1203 , H01L29/66621
摘要： A method for fabricating a semiconductor device includes forming an insulating pattern over a semiconductor substrate. An epitaxial growth layer is formed over the semiconductor substrate exposed by the insulating pattern to fill the insulating pattern with the epitaxial growth layer. A recess gate having a recess channel is formed. The recess channel is disposed between two neighboring insulating patterns.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底上形成绝缘图案。在由绝缘图案暴露的半导体衬底上形成外延生长层，以用外延生长层填充绝缘图案。形成具有凹槽的凹槽。凹槽通道设置在两个相邻绝缘图案之间。

2. 发明授权

US07358144B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07358144B2
公开(公告)日：2008-04-15
申请号：US11279164
申请日：2006-04-10
申请人： Song Hyeuk Im
发明人： Song Hyeuk Im
IPC分类号： H01L21/336
CPC分类号： H01L27/10885 , H01L27/10876 , H01L27/1203
摘要： A method for fabricating a semiconductor device includes forming first, second, and third device structures in a semiconductor substrate. Each device structure includes a first film, a second film over the first film, and a third film over the second film. The first and third device structures are device isolation structures. A portion of the second device structure is etched to define a bit line contact region, the bit line contact region extending from an upper surface of the second device structure to a lower surface of the second device structure. The second film of the second device structure is etched to define an under-cut space between the first and second films. A semiconductor layer is formed within the under-cut space and the bit line contact region. The third film of the second device structure is etched or removed to define a recess, the recess defining a gate region. A gate structure is formed at least partly within the recess.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底中形成第一，第二和第三器件结构。每个器件结构包括第一膜，第一膜上的第二膜和第二膜上的第三膜。第一和第三器件结构是器件隔离结构。蚀刻第二器件结构的一部分以限定位线接触区域，位线接触区域从第二器件结构的上表面延伸到第二器件结构的下表面。蚀刻第二器件结构的第二膜以限定第一和第二膜之间的下切空间。在下切割空间和位线接触区域内形成半导体层。蚀刻或去除第二器件结构的第三膜以限定凹部，凹部限定栅极区域。门结构至少部分地形成在凹槽内。

3. 发明申请

US20070264789A1 Semiconductor device having a device isolation trench 有权
标题翻译：具有器件隔离沟槽的半导体器件
公开(公告)号：US20070264789A1
公开(公告)日：2007-11-15
申请号：US11529354
申请日：2006-09-29
申请人： Song Hyeuk Im
发明人： Song Hyeuk Im
IPC分类号： H01L21/76 , H01L21/20
CPC分类号： H01L29/785 , H01L21/823437 , H01L29/66621 , H01L29/66795
摘要： A method for manufacturing a semiconductor device includes forming a semiconductor substrate to have a SOI structure by an epitaxial process for forming a gate while forming an insulating film pattern in a bottom where a device isolation trench is formed. The method thereby increases the process margin for forming a device isolation film and prevents the punch-through phenomenon to improve electrical characteristics of semiconductor devices and increase product yield.
摘要翻译：一种半导体器件的制造方法包括：在形成器件隔离沟槽的底部形成绝缘膜图案的同时，通过用于形成栅极的外延工艺形成具有SOI结构的半导体衬底。因此，该方法增加了用于形成器件隔离膜的工艺余量，并且防止穿通现象改善半导体器件的电特性并提高产品产量。

4. 发明授权

US08674473B2 Semiconductor cell and method for forming the same 有权
标题翻译：半导体电池及其形成方法
公开(公告)号：US08674473B2
公开(公告)日：2014-03-18
申请号：US13210909
申请日：2011-08-16
申请人： Song Hyeuk Im
发明人： Song Hyeuk Im
IPC分类号： H01L21/70
CPC分类号： H01L27/10855 , H01L21/764 , H01L21/7682 , H01L21/76831 , H01L21/76897 , H01L27/10885 , H01L27/11507
摘要： A semiconductor cell includes storage node contact plugs disposed on a semiconductor substrate, a bit line formation area which is disposed between the storage node contact plugs and exposes the semiconductor substrate, and an air gap which is in contact with a lower portion of a sidewall of the bit line formation area and extends in a direction perpendicular to a direction in which the bit line formation area extends. Therefore, the coupling effect between adjacent bit lines as well as the coupling effect caused between adjacent storage node contact plugs and the coupling effect caused between the storage node contact plug and the bit line are controlled to improve characteristics of semiconductor devices.
摘要翻译：半导体电池包括设置在半导体衬底上的存储节点接触插塞，位于存储节点接触插头之间并露出半导体衬底的位线形成区域，以及与侧壁的下侧接触的气隙位线形成区域并且在垂直于位线形成区域延伸的方向的方向上延伸。因此，控制相邻位线之间的耦合效应以及相邻存储节点接触插塞之间引起的耦合效应和存储节点接触插头与位线之间引起的耦合效应，以改善半导体器件的特性。

5. 发明申请

US20070173015A1 Method for Fabricating Semiconductor Device 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20070173015A1
公开(公告)日：2007-07-26
申请号：US11279164
申请日：2006-04-10
申请人： Song Hyeuk Im
发明人： Song Hyeuk Im
IPC分类号： H01L21/8242
CPC分类号： H01L27/10885 , H01L27/10876 , H01L27/1203
摘要： A method for fabricating a semiconductor device includes forming first, second, and third device structures in a semiconductor substrate. Each device structure includes a first film, a second film over the first film, and a third film over the second film. The first and third device structures are device isolation structures. A portion of the second device structure is etched to define a bit line contact region, the bit line contact region extending from an upper surface of the second device structure to a lower surface of the second device structure. The second film of the second device structure is etched to define an under-cut space between the first and second films. A semiconductor layer is formed within the under-cut space and the bit line contact region. The third film of the second device structure is etched or removed to define a recess, the recess defining a gate region. A gate structure is formed at least partly within the recess.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底中形成第一，第二和第三器件结构。每个器件结构包括第一膜，第一膜上的第二膜和第二膜上的第三膜。第一和第三器件结构是器件隔离结构。蚀刻第二器件结构的一部分以限定位线接触区域，位线接触区域从第二器件结构的上表面延伸到第二器件结构的下表面。蚀刻第二器件结构的第二膜以限定第一和第二膜之间的下切空间。在下切割空间和位线接触区域内形成半导体层。蚀刻或去除第二器件结构的第三膜以限定凹部，凹部限定栅极区域。门结构至少部分地形成在凹槽内。

6. 发明授权

US08338246B2 Method for fabricating a semiconductor device having a device isolation trench 有权
标题翻译：用于制造具有器件隔离沟槽的半导体器件的方法
公开(公告)号：US08338246B2
公开(公告)日：2012-12-25
申请号：US12571298
申请日：2009-09-30
申请人： Song Hyeuk Im
发明人： Song Hyeuk Im
IPC分类号： H01L21/8238
CPC分类号： H01L29/785 , H01L21/823437 , H01L29/66621 , H01L29/66795
摘要： A method for manufacturing a semiconductor device includes forming a semiconductor substrate to have a SOI structure by an epitaxial process for forming a gate while forming an insulating film pattern in a bottom where a device isolation trench is formed. The method thereby increases the process margin for forming a device isolation film and prevents the punch-through phenomenon to improve electrical characteristics of semiconductor devices and increase product yield.
摘要翻译：一种半导体器件的制造方法包括：在形成器件隔离沟槽的底部形成绝缘膜图案的同时，通过用于形成栅极的外延工艺形成具有SOI结构的半导体衬底。因此，该方法增加了用于形成器件隔离膜的工艺余量，并且防止穿通现象改善半导体器件的电特性并提高产品产量。

7. 发明授权

US08012833B2 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08012833B2
公开(公告)日：2011-09-06
申请号：US11966421
申请日：2007-12-28
申请人： Song Hyeuk Im
发明人： Song Hyeuk Im
IPC分类号： H01L21/336
CPC分类号： H01L21/823481 , H01L21/823437 , H01L21/84 , H01L27/1052 , H01L27/10876 , H01L27/1203 , H01L29/66621
摘要： A method for fabricating a semiconductor device includes forming an insulating pattern over a semiconductor substrate. An epitaxial growth layer is formed over the semiconductor substrate exposed by the insulating pattern to fill the insulating pattern with the epitaxial growth layer. A recess gate having a recess channel is formed. The recess channel is disposed between two neighboring insulating patterns.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底上形成绝缘图案。在由绝缘图案暴露的半导体衬底上形成外延生长层，以用外延生长层填充绝缘图案。形成具有凹槽的凹槽。凹槽通道设置在两个相邻绝缘图案之间。

8. 发明授权

US07601582B2 Method for manufacturing a semiconductor device having a device isolation trench 有权
标题翻译：一种具有器件隔离沟槽的半导体器件的制造方法
公开(公告)号：US07601582B2
公开(公告)日：2009-10-13
申请号：US11529354
申请日：2006-09-29
申请人： Song Hyeuk Im
发明人： Song Hyeuk Im
IPC分类号： H01L21/8238
CPC分类号： H01L29/785 , H01L21/823437 , H01L29/66621 , H01L29/66795
摘要： A method for manufacturing a semiconductor device includes forming a semiconductor substrate to have a SOI structure by an epitaxial process for forming a gate while forming an insulating film pattern in a bottom where a device isolation trench is formed. The method thereby increases the process margin for forming a device isolation film and prevents the punch-through phenomenon to improve electrical characteristics of semiconductor devices and increase product yield.
摘要翻译：一种半导体器件的制造方法包括：在形成器件隔离沟槽的底部形成绝缘膜图案的同时，通过用于形成栅极的外延工艺形成具有SOI结构的半导体衬底。因此，该方法增加了用于形成器件隔离膜的工艺余量，并且防止穿通现象改善半导体器件的电特性并提高产品产量。

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