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1. 发明授权

US06662272B2 Dynamic cache partitioning 有权
标题翻译：动态缓存分区
公开(公告)号：US06662272B2
公开(公告)日：2003-12-09
申请号：US09967614
申请日：2001-09-29
申请人： Sompong P. Olarig , Phillip M. Jones , John E. Jenne
发明人： Sompong P. Olarig , Phillip M. Jones , John E. Jenne
IPC分类号： G06F1208
CPC分类号： G06F12/084 , G06F12/12
摘要： A cache-based system is adapted for dynamic cache partitioning. A cache is partitioned into a plurality of cache partitions for a plurality of entities. Each cache partition can be assigned as a private cache for a different entity. If a first cache partition satisfying a first predetermined cache partition condition and a second cache partition satisfying a second predetermined cache partition condition are detected, then the size of the first cache partition is increased by a predetermined segment and the size of the second cache partition is decreased by the predetermined segment. An entity can perform cacheline replacement exclusively in its assigned cache partition, and also be capable of reading any cache partition.
摘要翻译：基于缓存的系统适用于动态高速缓存分区。高速缓存被分割成多个实体的多个高速缓存分区。每个缓存分区可以分配为不同实体的专用缓存。如果检测到满足第一预定高速缓存分区条件的第一缓存分区和满足第二预定高速缓存分区条件的第二高速缓存分区，则第一高速缓存分区的大小增加预定分段，并且第二高速缓存分区的大小为减少预定段。实体可以在其分配的高速缓存分区中专门执行高速缓存行替换，并且还可以读取任何高速缓存分区。

2. 发明授权

US06865647B2 Dynamic cache partitioning 有权
标题翻译：动态缓存分区
公开(公告)号：US06865647B2
公开(公告)日：2005-03-08
申请号：US10730761
申请日：2003-12-08
申请人： Sompong P. Olarig , Phillip M. Jones , John E. Jenne
发明人： Sompong P. Olarig , Phillip M. Jones , John E. Jenne
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/084 , G06F12/12
摘要： A cache-based system is adapted for dynamic cache partitioning. A cache is partitioned into a plurality of cache partitions for a plurality of entities. Each cache partition can be assigned as a private cache for a different entity. If a first cache partition satisfying a first predetermined cache partition condition and a second cache partition satisfying a second predetermined cache partition condition are detected, then the size of the first cache partition is increased by a predetermined segment and the size of the second cache partition is decreased by the predetermined segment. An entity can perform cacheline replacement exclusively in its assigned cache partition, and also be capable of reading any cache partition.
摘要翻译：基于缓存的系统适用于动态高速缓存分区。高速缓存被分割成多个实体的多个高速缓存分区。每个缓存分区可以分配为不同实体的私有缓存。如果检测到满足第一预定高速缓存分区条件的第一缓存分区和满足第二预定高速缓存分区条件的第二高速缓存分区，则第一高速缓存分区的大小增加预定分段，并且第二高速缓存分区的大小为减少预定段。实体可以在其分配的高速缓存分区中专门执行高速缓存行替换，并且还可以读取任何高速缓存分区。

3. 发明授权

US06370657B1 Hot processor swap in a multiprocessor personal computer system 有权
标题翻译：多处理器个人计算机系统中的热处理器交换
公开(公告)号：US06370657B1
公开(公告)日：2002-04-09
申请号：US09196264
申请日：1998-11-19
申请人： Kenneth A. Jansen , Sompong P. Olarig , John E. Jenne
发明人： Kenneth A. Jansen , Sompong P. Olarig , John E. Jenne
IPC分类号： G06F1100
CPC分类号： G06F11/0793 , G06F11/0724 , G06F13/4081
摘要： A scheme may be used to remove or replace a processor in a multiprocessor computer without the need for turning the computer off to replace the processor. In this scheme, the bus to which the processor is coupled is identified so that all processors coupled to the bus may be placed in sleep mode. This act does not alter the normal operation of processors that may be coupled to another bus. Once the processors are in sleep mode, the processor may be removed or replaced. Afterward, all processors may be returned to normal operation.
摘要翻译：可以使用方案来移除或替换多处理器计算机中的处理器，而不需要关闭计算机来替换处理器。在该方案中，识别处理器耦合到的总线，使得耦合到总线的所有处理器可以被置于睡眠模式。该动作不会改变可能耦合到另一总线的处理器的正常操作。一旦处理器处于睡眠模式，处理器可能会被删除或更换。之后，所有处理器都可以恢复正常运行。

4. 发明授权

US06631440B2 Method and apparatus for scheduling memory calibrations based on transactions 失效
标题翻译：基于事务调度存储器校准的方法和装置
公开(公告)号：US06631440B2
公开(公告)日：2003-10-07
申请号：US09726739
申请日：2000-11-30
申请人： John E. Jenne , Sompong P. Olarig
发明人： John E. Jenne , Sompong P. Olarig
IPC分类号： G06F1300
CPC分类号： G06F13/161
摘要： A computer system includes a memory controller that controls and formats transactions with a high speed memory. The memory controller includes a read queue, a write queue, and various other queues in which memory transactions may be stored pending execution. The memory controller periodically executes calibration cycles, such as temperature calibration cycles to the memory to reduce memory errors. The temperature calibration cycles may include an idle state during which no read transactions can be executed. The memory controller includes arbitration logic that reduces latency by issuing read transaction first. Once reads have been issued, the arbitration logic executes any pending temperature cycles. During the idle period of the calibration cycle, the arbitration logic schedules write transactions, and transactions to memory from other queues and devices, including precharge transactions, row activate transactions, refresh cycles, and other calibration cycles.
摘要翻译：计算机系统包括控制和格式化与高速存储器的事务的存储器控制器。存储器控制器包括读队列，写队列和其中可存储待执行的存储器事务的各种其他队列。存储器控制器周期性地执行校准周期，例如到存储器的温度校准周期以减少存储器错误。温度校准周期可以包括空闲状态，在此状态期间不能执行读取事务。存储器控制器包括通过首先发出读取事务来减少等待时间的仲裁逻辑。一旦读取被发出，仲裁逻辑执行任何未决的温度循环。在校准周期的空闲周期期间，仲裁逻辑将写入事务和来自其他队列和设备的存储器的事务调度，包括预充电事务，行激活事务，刷新周期和其他校准周期。

5. 发明授权

US06493836B2 Method and apparatus for scheduling and using memory calibrations to reduce memory errors in high speed memory devices 有权
公开(公告)号：US06493836B2
公开(公告)日：2002-12-10
申请号：US09726738
申请日：2000-11-30
申请人： Sompong P. Olarig , John E. Jenne
发明人： Sompong P. Olarig , John E. Jenne
IPC分类号： G06F1130
CPC分类号： G11C29/44 , G06F11/076 , G06F11/10 , G11C11/401 , G11C29/028 , G11C2029/0409 , G11C2029/4402
摘要： A computer system with high-speed memory devices includes error checking logic that monitors the number and/or frequency of memory errors. The number and/or frequency of soft memory errors is provided to control logic in a memory controller, which intelligently modifies the frequency of memory calibration cycles based on the detected memory errors. Thus, in response to an unacceptable number of memory errors, the memory controller may increase the frequency of calibration cycles. The memory controller may include error checking logic that monitors memory errors on multiple memory channels, if multiple memory channel are provided, to enable the memory controller to modify calibration frequency on a channel-by-channel basis.

6. 发明授权

US06467048B1 Apparatus, method and system for using cache memory as fail-over memory 失效
标题翻译：使用高速缓冲存储器作为故障切换存储器的装置，方法和系统
公开(公告)号：US06467048B1
公开(公告)日：2002-10-15
申请号：US09414206
申请日：1999-10-07
申请人： Sompong P. Olarig , John E. Jenne , Christopher M. Carbajal
发明人： Sompong P. Olarig , John E. Jenne , Christopher M. Carbajal
IPC分类号： H02H305
CPC分类号： G11C29/70 , G06F12/0802
摘要： A computer system having a main memory and a cache memory, the computer system uses portions of the cache memory to store information from defective main memory locations until the main memory can be repaired. The address space of the main memory is always maintained by substituting cache-lines of cache memory for the defective main memory locations. A fail-over memory status bit in the cache memory controller indicates when a cache line of the cache memory contains fail-over information from the defective or failing main memory so that that cache-line will not be written over by a cache replacement algorithm. When the fail-over status bit is set, the contents of the fail-over memory location(s) remains in the cache-line and all memory reads and writes are directed to only that cache-line of the cache memory and not the main memory for the fail-over memory location(s). Also no write-back of the fail-over memory location(s) from cache memory to the main memory is required nor desired until the main memory location is repaired or replaced. Indicator lights may be used to represent the different activities of the main and cache memories at detection of the defective memory location, during and after fail-over from the main memory location to the cache-line, and transfer back to the main memory once repaired. A plurality of cache memories may migrate fail-over information therebetween.
摘要翻译：一种具有主存储器和高速缓冲存储器的计算机系统，该计算机系统使用高速缓冲存储器的部分来存储来自有缺陷的主存储器位置的信息，直到可以修复主存储器。主存储器的地址空间总是通过用高速缓冲存储器的高速缓存行代替有缺陷的主存储器位置来维护。高速缓冲存储器控制器中的故障切换存储器状态位指示高速缓冲存储器的高速缓存行何时包含来自故障或故障主存储器的故障切换信息，使得该高速缓存行将不被高速缓存替换算法写入。当故障转移状态位置1时，故障转移存储器位置的内容保留在高速缓存行中，并且所有存储器读取和写入仅定向到缓存存储器的高速缓存行，而不是主存储器用于故障切换存储器位置的存储器。也不需要直到主存储器位置被修复或更换才能将故障切换存储器位置从高速缓冲存储器写回主存储器。在从主存储器位置到高速缓存行的故障转移期间和之后检测到缺陷存储器位置时，指示灯可用于表示主存储器和高速缓冲存储器的不同活动，并且一旦修复就返回到主存储器。多个高速缓冲存储器可以迁移它们之间的故障切换信息。

7. 发明授权

US06360333B1 Method and apparatus for determining a processor failure in a multiprocessor computer 有权
标题翻译：用于确定多处理器计算机中的处理器故障的方法和装置
公开(公告)号：US06360333B1
公开(公告)日：2002-03-19
申请号：US09196463
申请日：1998-11-19
申请人： Kenneth A. Jansen , Sompong P. Olarig , John E. Jenne
发明人： Kenneth A. Jansen , Sompong P. Olarig , John E. Jenne
IPC分类号： G06F1100
CPC分类号： G06F11/2236 , G06F11/202 , G06F11/2035 , G06F11/2046
摘要： A multiprocessor computer includes a fault detection scheme which detects and identifies the failure of one of the processors. Each processor is assigned a write location, which may be a unique register. During normal computer operation, each processor intermittently performs a test and stores the results of the test in the assigned write location. The stored results are compared to expected results, and an error signal is generated if the stored results differ from the expected results to indicate that one of the processors has failed.
摘要翻译：多处理器计算机包括检测并识别其中一个处理器的故障的故障检测方案。每个处理器被分配一个写入位置，它可以是唯一的寄存器。在正常的计算机操作期间，每个处理器间歇地执行测试并将测试结果存储在分配的写入位置中。将存储的结果与预期结果进行比较，如果存储的结果与预期结果不同，则生成错误信号，以指示其中一个处理器发生故障。

8. 发明授权

US06792553B2 CPU power sequence for large multiprocessor systems 有权
标题翻译：大型多处理器系统的CPU电源顺序
公开(公告)号：US06792553B2
公开(公告)日：2004-09-14
申请号：US09751506
申请日：2000-12-29
申请人： Clarence Y. Mar , Sompong P. Olarig , John E. Jenne
发明人： Clarence Y. Mar , Sompong P. Olarig , John E. Jenne
IPC分类号： G06F126
CPC分类号： G06F1/305 , G06F1/26
摘要： A computer system includes a power supply coupled to a control logic, the power supply including a power_good output signal and Power output lines. The power_good signal notifies the control logic when the Power output lines have stabilized. The computer system also includes a plurality of voltage regulator modules (“VRM”) coupled to the control logic, wherein each VRM receives a power good signal from the control logic. A plurality of processors is also present in the computer system, each of the processors coupled to a VRM. Each of the VRMs transmits voltage to a processor to power-on the processor. Each VRM also transmits to its processor and to the control logic a voltage regulator module power good (“VRMP_G”) signal. The control logic includes means to control the sequential power-on of the processors so as to reduce the current sourcing requirements of the power supply and eliminate power supply surges.
摘要翻译：计算机系统包括耦合到控制逻辑的电源，电源包括power_good输出信号和电力输出线。当电源输出线路稳定时，power_good信号通知控制逻辑。计算机系统还包括耦合到控制逻辑的多个电压调节器模块（“VRM”），其中每个VRM从控制逻辑接收功率良好信号。计算机系统中还存在多个处理器，每个处理器耦合到VRM。每个VRM将电压传输到处理器以对处理器通电。每个VRM还向其处理器和控制逻辑发送电压调节器模块电源良好（“VRMP_G”）信号。控制逻辑包括用于控制处理器的顺序上电的装置，以便减少电源的电流采购要求并消除电源浪涌。

9. 发明授权

US06564288B2 Memory controller with temperature sensors 有权
公开(公告)号：US06564288B2
公开(公告)日：2003-05-13
申请号：US09726825
申请日：2000-11-30
申请人： Sompong P. Olarig , John E. Jenne
发明人： Sompong P. Olarig , John E. Jenne
IPC分类号： G11C11406
CPC分类号： G06F1/206
摘要： A computer system with high-speed memory devices includes one or more temperature sensors and/or environmental sensors that monitor environmental parameters that may affect the operation of the high-speed memory devices. The sensor values are provided to a control logic in a memory controller, that can intelligently modify the operation of the memory devices in response to changing environmental conditions. Thus, in response to deteriorating environmental conditions, the memory controller may increase the frequency of calibration cycles, or may throttle down the operating speed of the memory devices, or may place some or all of the memory devices in a low power mode until conditions improve. The sensors may be provided on multiple channels, if the memory system is configured with multiple channels, or may be individually associated with memory devices.

10. 发明授权

US06484232B2 Adaptive calibration technique for high speed memory devices 有权
标题翻译：高速存储器件的自适应校准技术
公开(公告)号：US06484232B2
公开(公告)日：2002-11-19
申请号：US09727861
申请日：2000-11-30
申请人： Sompong P. Olarig , John E. Jenne
发明人： Sompong P. Olarig , John E. Jenne
IPC分类号： G06F1130
CPC分类号： G11C5/06 , G06F13/1694 , G11C5/04 , G11C7/04 , G11C7/1045 , G11C7/1072 , G11C11/4078 , G11C2207/2254
摘要： A computer system with high-speed memory devices includes one or more temperature sensors and/or environmental sensors that monitor environmental parameters that may affect the operation of the high-speed memory devices. The sensor values are provided to control logic in a memory controller that can intelligently modify the operation of the memory devices in response to changing environmental conditions. Thus, in response to deteriorating environmental conditions, the memory controller may increase the frequency of calibration cycles. The sensors may be provided on multiple channels, if the memory system is configured with multiple channels, or may be individually associated with memory devices. In addition, the memory controller also monitors the expected remaining life of the memory devices, and the number of errors occurring in the memory devices, and based on these parameters, may change the frequency of the calibration cycles.
摘要翻译：具有高速存储器装置的计算机系统包括一个或多个温度传感器和/或环境传感器，其监测可能影响高速存储器件的操作的环境参数。将传感器值提供给存储器控制器中的控制逻辑，其可以根据变化的环境条件智能地修改存储器件的操作。因此，响应于恶化的环境条件，存储器控制器可以增加校准周期的频率。如果存储器系统配置有多个通道，或者可以单独地与存储器件相关联，则传感器可以设置在多个通道上。此外，存储器控制器还监视存储器件的期望的剩余寿命，并且存储器件中出现的错误的数量，并且基于这些参数，可以改变校准周期的频率。

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